Test Bench - 4.2 English

JESD204C LogiCORE IP Product Guide (PG242)

Document ID
PG242
Release Date
2023-11-06
Version
4.2 English

The example design supplied with the JESD204C core provides a complete simulation environment including a demonstration test bench that allows you to simulate the core, and view the inputs and outputs using the AMD Vivado™ Design Suite.

The test bench instantiates the example design described in Design Flow Steps, and provides the necessary stimulus to show the example design functioning. The test bench can be run at all stages of the design process from behavioral simulation of the RTL code through full post-implementation timing simulation.

The following figure shows an overview of the test bench delivered with the example design.

Figure 1. Core Demo Test Bench Page-1 Sheet.1 Sheet.2 Sheet.3 Example Design Example Design Sheet.9 TX TX Sheet.10 RX RX Sheet.12 Main Test Task MainTest Task Sheet.13 Sheet.16 CLK RST SYSREF Generator CLKRSTSYSREFGenerator Sheet.17 Sheet.22 AXI4-Lite Stim Tasks AXI4-LiteStim Tasks Sheet.23 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.45 X20359-060320 X20359-060320