Port Name | Interface | I/O | Description |
---|---|---|---|
tx_core_clk |
System s_axis_tx s_axis_tx_cmd |
I | Core logic clock input. Frequency: Serial line rate / 66 (for 64B66B linecoding) Serial line rate / 40 (for 8B10B linecoding) |
tx_core_reset | System | I | Core asynchronous logic reset active-High. |
tx_aresetn | s_axis_tx s_axis_tx_cmd | O | AXI4-Stream interface reset. Active-Low. Associated with both data and command interfaces. |
s_axi_aclk | s_axi | I | AXI4-Lite clock input. |
s_axi_aresetn | s_axi | I | AXI4-Lite reset input. Active-Low. |
s_axi* | s_axi | I | See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for a description of AXI4 signals. |
irq | System | O | System interrupt output. |
tx_sysref | System | I | SYSREF input. When Subclass 1 mode is selected, this signal is required and used by the core to set the phase of the local extended multi-block clock. This SYSREF signal must be generated synchronous to the core clock. This input should be driven from an external device generating SYSREF for both TX and RX on a link. |
tx_sync | System | I | Sync signal. The sync signal is defined as an active-Low sync request signal by JESD204 so this signal is Low until comma alignment is completed and High to request ILA and normal data. This signal is only available when the core is generated with 8B10B linecoding selected. |
Versal Adaptive SoCs | |||
gt_powergood 1 | System | I | This active-High signal from Versal Adaptive SoC Transceiver indicates when the GT clocking resources have completed power up. |
gt_loopback[2:0] 1 | System | O | This signal to the Versal Adaptive SoC Transceiver controls the various loopback modes. This must be connected to the chN_loopback[2:0] port in the CHn_DEBUG interface of the GT Quad. |
txusrclk 1 | System | I | Versal Adaptive SoC GTM 66-bit clock used for 64b66b encoder gearbox (GTM only). |
AMD UltraScale+™ /AMD UltraScale™ Devices | |||
tx_reset_gt | System | O | JESD204_PHY TX datapath reset. Core output to reset the transmit datapath in a connected JESD204_PHY. This must be connected to a JESD204_PHY. |
tx_reset_done | System | I | JESD204_PHY TX reset done input. Indicates the JESD204_PHY has completed the transmit reset process. |
|
Signal Name | Interface | I/O | Description |
---|---|---|---|
chN_txctrl0[15:0] | GT_TX | O | TX Disparity control to the Versal Adaptive SoC Transceiver. N = Lanes -1 |
chN_txctrl1[15:0] | GT_TX | O | TX Disparity polarity control to the Versal Adaptive SoC Transceiver. N = Lanes -1 |
chN_txctrl2[7:0] | GT_TX | O | TX Char is K to the Versal Adaptive SoC Transceiver. N = Lanes -1 |
chN_txdata[127:0] 3 | GT_TX | O | TX Data to the Versal
Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txdiffctrl[4:0] | GT_TX | O | TX diffctrl to the Versal
Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txelecidle | GT_TX | O | TX txelecidle to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txheader[5:0] | GT_TX | O | TX Header to the Versal
Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txinhibit | GT_TX | O | TX Inhibit to the Versal
Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txmaincursor[6:0] | GT_TX | O | TX Main-cursor pre-emphasis control to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txmstdatapathreset | GT_TX | O | TX Master Datapath only Reset sequence start to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txmstreset | GT_TX | O | TX Master Reset sequence start to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txmstresetdone | GT_TX | I | TX Master Reset sequence Done to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txpd[1:0] | GT_TX | O | TX Power Down to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txpmaresetdone | GT_TX | I | TX PMA Reset Done from the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txpolarity | GT_TX | O | TX Polarity control to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txpostcursor[5:0] | GT_TX | O | TX Post-cursor pre-emphasis control to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txprbssel[3:0] | GT_TX | O | TX PRBS Select to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txprecursor[5:0] | GT_TX | O | TX Pre-cursor pre-emphasis control to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txprecursor2[5:0] | GT_TX | O | TX Pre-cursor pre-emphasis control to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txprecursor3[5:0] | GT_TX | O | TX Pre-cursor pre-emphasis control to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txrate[7:0] | GT_TX | O | TX Line Rate Control to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txsequence[6:0] | GT_TX | O | TX Sequence Counter to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
chN_txuserrdy | GT_TX | O | TX User clocks stable to the Versal Adaptive SoC Transceiver. N = Lanes - 1 |
|
Signal Name | Interface | I/O | Description |
---|---|---|---|
gtN_txdata[63:0] | PHY | O | TX data to JESD204 PHY. N = Lanes - 1 |
gtN_txheader[1:0] | PHY | O | TX header to JESD204 PHY. N = Lanes - 1 |
gtN_txcharisk[3:0] | PHY | O | TX Char is K to JESD204 PHY. N = Lanes -1 |
Signal Name | Interface | I/O | Description |
---|---|---|---|
tx_tdata [(64*N)-1:0] | s_axis_tx | I | Transmit data input. N = Lanes |
tx_tready | s_axis_tx | O | AXI4-Stream tready |
tx_soemb | s_axis_tx | O |
Start of extended multi-block boundary indication. Set to 1 to indicate tx_tdata in the following clock cycle is the start of an extended multi-block. |
tx_cmd_tdata[(32*N)-1:0] | s_axis_tx_cmd | I | Transmit Cmd interface. N = Lanes For Meta mode = CRC, Cmd payload is bits [6:0] with bits [31:7] set to zero. For Meta mode = CMD, Cmd payload is [18:0] with bits [31:19] set to zero |
tx_cmd_tvalid | s_axis_tx_cmd | I | AXI4-Stream tvalid. |
tx_cmd_tready | s_axis_tx_cmd | O | AXI4-Stream tready. tx_cmd_tready will be set for one cycle every multi-block to control the Cmd word flow. |
Signal Name | Interface | I/O | Description |
---|---|---|---|
tx_tdata [(32*N)-1:0] | s_axis_tx | I | Transmit data input. N = Lanes |
tx_tready | s_axis_tx | O | AXI4-Stream tready |
tx_sof [3:0] | s_axis_tx | O |
Start of frame boundary indication. The signal is four bits to indicate the byte position of the first byte of a frame in tdata in the following clock cycle.
Note: Multiple bits of tx_sof can
be asserted in the same cycle, depending on the number of octets per frame.
For example, for a frame size of two octets and tx_sof = 0101, the first and third bytes (bits[7:0] and bits[23:16]) of the tdata word contain the first bytes of frames. |
tx_somf [3:0] | s_axis_tx | O |
Start of multiframe boundary indication. The position of the first byte of each multiframe is encoded in the same way as tx_sof. |