Step 2: Calculate the End to End Latency Using N - 4.3 English - PG242

The data is received after N LMFC periods and before N+1 LMFC periods so the min deterministic latency is T plus one LMFC plus the fixed input delay at the FPGA and the fixed output delay at the DAC:

T_LAT = (T + LMFC) + T_TXIN + T_RXOUT

Substituting (N*LMFC - T_TXLMFC + T_RXLMFC) for T gives:

T_LAT = ((N*LMFC - T_TXLMFC + T_RXLMFC) + LMFC) + T_RXOUT + T_TXIN

= (N+1)*LMFC - T_TXLMFC + T_RXLMFC + T_TXIN + T_RXOUT