For JESD204C, the most generic and flexible clocking scheme uses separate transceiver reference and JESD204C core clocks supplied to the FPGA. In this configuration, the reference and core clocks are physically separate and can be run at independent, but related, frequencies, without additional constraints.
The reference clock can be run at any frequency within the limitations of the transceiver for the selected line rate. The core clock always runs at the required rate (1/66th or 1/40th of the serial line rate). This configuration is shown in the following two figures for 64B66B and 8B10B line coding.
Figure 1. Separate Transceiver Reference and Core Clocks: 64B66B Example for Versal Adaptive SoCs
Figure 2. Separate Transceiver Reference Clock and Core Clock: 8B10B Example for
Versal Adaptive SoCs
Figure 3. Separate Transceiver Reference and Core Clocks: 64B66B Example for UltraScale+/UltraScale Devices
Figure 4. Separate Transceiver Reference Clock and Core Clock: 8B10B Example for
UltraScale+/UltraScale Devices
