When the JESD204C is used in Subclass 1, the SYSREF signal is the master timing reference for the system. To achieve
accurate deterministic latency, the SYSREF signal must
be captured synchronously to the core clock. To achieve this, the SYSREF period must be
a multiple of 4-byte clock periods for 8B10B linecoding and 8-byte clock periods for
64B66B linecoding. This is because the core uses a 4-byte or 8-byte internal datapath
for 8B10B and 64B66B, respectively.