Revision History - Revision History - 4.3 English - PG242

JESD204C v4.3 LogiCORE IP Product Guide (PG242)
Document ID
PG242
Release Date
2025-12-03
Version
4.3 English

The following table shows the revision history for this document.

Section Revision Summary
12/03/2025 Version 4.3
Data and Command Interfaces

Updated the 8B10B and 64B66B encoding timing diagrams for clarity.
Capturing SYSREF Updated the SYSREF timing diagram and added a note to it.
User Parameters Updated the user parameters table to change the default value of Select GT Wizard Type from 0 - Legacy_GT_Wizard to 1 - GT WIZARD SUBSYSTEM.
Combining Multiple JESD204C Cores Added this section.
12/11/2024 Version 4.3
General updates

Updated to include the new GT Wizard subsystem.
Using Multiple JESD204C Cores to Connect to One or More ADCs Across SLR Boundaries Added this section.
11/06/2023 Version 4.2
General updates

Added images.
Register Space
  • Added CTRL_PRBS_MODE to CTRL_TEST_MODE register for 64B66B and 8B10B
  • Added Table 55: CTRL TX VERSAL GTY/GTYP
  • Added Table 56: CTRL TX VERSAL GTM
02/01/2023 Version 4.2
TX Core Added encoder_rst port for Versal GTM 64B66B designs.
RX Core Added decoder_rst port for Versal GTM 64B66B designs.
Separate Transceiver Reference and Core Clocks Changed clock frequencies to reflect higher Versal line rates.
Receive Latency Added topic.
RX End to End Latency Added topic.
ADC Timing Added topic for 8B10B RX latency.
Core Timing Added topic for 8B10B RX latency.
Calculating End to End Latency Added topic for 8B10B RX latency.
ADC Timing Added topic for 64B66B RX latency.
Core Timing Added topic for 64B66B RX latency.
Calculating End to End Latency Added topic for 64B66B RX latency.
Transmit Latency Added topic.
TX End to End Latency Added topic for 8B10B TX latency.
Core Timing Added topic for 8B10B TX latency.
DAC Timing Added topic for 8B10B TX latency.
Calculating End to End Latency Added topic for 8B10B TX latency.
Core Timing Added topic for 64B66B TX latency.
DAC Timing Added topic for 64B66B TX latency.
Calculating End to End Latency Added topic for 64B66B TX latency.
06/10/2022 Version 4.2
Clocking

Added 8B10B and 64B66B support with Versal adaptive SoC GTM transceivers.
03/25/2021 Version 4.2
Example Designand Connecting to Transceivers Using Block Automation for Versal Adaptive SoCs
  • Removed the encommaalign_AXI4l block from the Versal adaptive SoC example designs.
  • Added Customized Connections option information for block automation.
07/16/2020 Version 4.2
General updates

Added support for Versal devices.
06/03/2020 Version 4.2
Configuring the JESD204 PHY in IP Integrator for UltraScale+/UltraScale Devices
  • Added support for GTHE3 and GTHE4 transceivers.
05/22/2019 Version 4.1
SYSREF
  • Added tolerance radius for SYSREF in SYSREF always mode.
  • Added configurable lanes per link register.
11/14/2018 Version 4.0
Example Design
  • Modified TX and RX CMD AXI4-Stream tdata ports to be 32-bits per lane.
  • Modified example design.
  • Added configuration bits to identify if core was generated with FEC included.
04/04/2018 Version 3.0
Core Clock 8B10B Linecoding

Added 8B10B linecoding mode.
10/4/2017 Version 2.0
General updates
  • Added ports: gtN_txcharisk[3:0], gtN_rxcharisk[3:0], gtN_rxdisperr[3:0], gtN_rxnotintable[3:0]
  • Removed reference to individual parts of JESD204C specification.
06/07/2017 Version 1.0
Clocking Added GT_POWERGOOD from JESD204_PHY to clocking example description and figure 3-2.
04/05/2017 Version 1.0
Initial release. N/A