The reset inputs and outputs on the JESD204C core are as shown in the following table.
| Reset | Description |
|---|---|
| tx/rx_core_reset | This reset input is asynchronous and active-High. This reset input will reset the JESD204C core logic but does not reset the AXI4-Lite register interface, so all programmed register values will be maintained. |
| s_axi_aresetn | This reset input must be synchronized with the AXI4-Lite
interface clock. This reset input will reset the AXI4-Lite register interface. |
| tx/rx_aresetn | This reset output is synchronous to tx/rx_core_clk. This output is an AXI4-Stream interface reset signal to be used with the AXI4-Stream RX/TX Data and Cmd interfaces. |
| Versal Adaptive SoCs | |
| chN_txmstdatapathreset | This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation.
The output is driven by internal logic in the JESD204C core. N = Lanes - 1 |
| chN_txmstreset | This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation. The output is
driven by internal logic in the JESD204C core. N = Lanes - 1 |
| chN_txpmaresetdone | This active-High reset input is connected to the Versal Adaptive SoC Transceiver using Block Automation.
The input holds the JESD204C core in reset until it asserts High. N = Lanes - 1 |
| chN_txuserrdy | This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation.
The output is driven by internal logic in the JESD204C core. N = Lanes - 1 |
| chN_txmstresetdone | This active-High reset input is connected to the Versal Adaptive SoC Transceiver using Block Automation.
The input holds the JESD204C core in reset until it asserts High. N = Lanes - 1 |
| chN_rxmstdatapathreset | This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation. The output is
driven by internal logic in the JESD204C core. N = Lanes - 1 |
| chN_rxmstreset | This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation.
The output is driven by internal logic in the JESD204C core. N = Lanes - 1 |
| chN_rxpmaresetdone | This active-High reset input is connected to the Versal Adaptive SoC Transceiver using Block Automation.
The input holds the JESD204C core in reset until it asserts High. N = Lanes - 1 |
| chN_rxuserrdy | This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation.
The output is driven by internal logic in the JESD204C core. N = Lanes - 1 |
| chN_rxmstresetdone | This active-High reset input is connected to the Versal Adaptive SoC Transceiver using Block Automation.
The input holds the JESD204C core in reset until it asserts High. N = Lanes - 1 |
| UltraScale+/UltraScale Devices | |
| tx/rx_reset_gt | This reset output must be connected to the JESD204_PHY core. This signal is used to initiate a JESD204_PHY GT reset sequence. |
| tx/rx_reset_done | This input must be connected to the JESD204_PHY core. This signal is used to hold the JESD204C core in reset until completion of the JESD204_PHY GT reset sequence. Note: A Low input on this port will force the JESD204C core into a
reset state.
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