Register Space - 4.2 English

JESD204C LogiCORE IP Product Guide (PG242)

Document ID
PG242
Release Date
2023-11-06
Version
4.2 English

The JESD204C core is configured using an AXI4-Lite Register Interface. The register map is shown in the following table.

The RX and TX cores share a common address map and register definitions where possible, exceptions are highlighted.

Table 1. Register Address Space
AXI4-Lite Address Register Name 64B66B 8B10B
TX Access Type RX Access Type TX Access Type RX Access Type
0x000 IP_VERSION R R R R
0x004 IP_CONFIG R R R R
0x020 RESET RW RW RW RW
0x024 CTRL_ENABLE RW RW N/A N/A
0x028 CTRL_TX_SYNC N/A N/A RW N/A
0x030 CTRL_MB_IN_EMB RW RW N/A N/A
0x034 CTRL_SUB_CLASS RW RW RW RW
0x038 CTRL_META_MODE RW RW N/A N/A
0x03C CTRL_8B10B_CFG N/A N/A RW RW
0x040 CTRL_LANE_ENA RW RW RW RW
0x044 CTRL_RX_BUF_ADV N/A RW N/A RW
0x048 CTRL_TEST_MODE RW RW RW RW
0x04C CTRL_RX_MBLOCK_TH N/A RW N/A N/A
0x050 CTRL_SYSREF RW RW RW RW
0x054 STAT_LOCK_DEBUG N/A R N/A N/A
0x058 STAT_RX_ERR N/A N/A N/A R
0x05C STAT_RX_DEBUG N/A N/A N/A R
0x060 STAT_STATUS R R R R
0x064 CTRL_IRQ RW RW RW RW
0x068 STAT_IRQ R R R R
0x070 CTRL_TX_ILA_CFG0 N/A N/A RW N/A
0x074 CTRL_TX_ILA_CFG1 N/A N/A RW N/A
0x078 CTRL_TX_ILA_CFG2 N/A N/A RW N/A
0x07C CTRL_TX_ILA_CFG3 N/A N/A RW N/A
0x080 CTRL_TX_ILA_CFG4 N/A N/A RW N/A
0x400 1 (Lane 0) STAT_RX_BUF_LVL N/A R N/A R
0x404 1 (Lane 0) CTRL_TX_ILA_LID N/A N/A RW N/A
0x410 1 (Lane 0) STAT_RX_ERROR_CNT0 N/A R N/A N/A
0x414 1 (Lane 0) STAT_RX_ERROR_CNT1 N/A R N/A N/A
0x420 1 (Lane 0) STAT_LINK_ERR_CNT N/A N/A N/A R
0x424 1 (Lane 0) STAT_TEST_ERR_CNT N/A N/A N/A R
0x428 1 (Lane 0) STAT_TEST_ILA_CNT N/A N/A N/A R
0x42C 1 (Lane 0) STAT_TEST_MF_CNT N/A N/A N/A R
0x430 1 (Lane 0) CTRL_RX_ILA_CFG0 N/A N/A N/A R
0x434 1 (Lane 0) CTRL_RX_ILA_CFG1 N/A N/A N/A R
0x438 1 (Lane 0) CTRL_RX_ILA_CFG2 N/A N/A N/A R
0x43C 1 (Lane 0) CTRL_RX_ILA_CFG3 N/A N/A N/A R
0x440 1 (Lane 0) CTRL_RX_ILA_CFG4 N/A N/A N/A R
0x444 1 (Lane 0) CTRL_RX_ILA_CFG5 N/A N/A N/A R
0x448 1 (Lane 0) CTRL_RX_ILA_CFG6 N/A N/A N/A R
0x44C 1 (Lane 0) CTRL_RX_ILA_CFG7 N/A N/A N/A R
0x460 1 (Lane 0) CTRL_TX_GT RW RW RW RW
0X464 1 (Lane 0) CTRL_RX_GT RW RW RW RW
0X468 1 (Lane 0) CTRL_TX_VERSAL_GTY/GTYP RW RW RW RW
0X46C 1 (Lane 0) CTRL_TX_VERSAL_GTM RW RW RW RW
  1. As shown, lane 0 registers start at 0x400. Lane 1 registers occupy the equivalent space starting at 0x480, lanes 2-7 follow the same pattern (that is, lane 2 = 0x500, lane 3 = 0x580, etc.).
Table 2. IP_VERSION
Bits Default Value Description
31:24 Version: Major
23:16 Version: Minor
15:8 Version: Revision
7:0 Reserved (read 0x00)
Table 3. IP_CONFIG
Bits Default Value Description
18 1= FEC Included

0=FEC not included

(FEC is only available when configured for 64B66B)

17 1 = Core is 64B66B

0 = Core is 8B10B

16 1 = Core is TX

0 = Core is RX

3:0 Number of lanes in core.
Table 4. RESET
Bits Default Value Description
31:24 1 gt_mst_reset_busy[7:0]

1-bit per enabled GT lane. These bits show the inversion of the mstresetdone inputs from the Versal adaptive SoC GTs.

23:16 1 gt_pma_reset_busy[7:0]

1-bit per enabled GT lane. These bits show the inversion of the pmaresetdone inputs from the Versal adaptive SoC GTs.

7 gt_reset_busy

1 = GTs are still in reset

0 = GTs have finished reset

6 1 gt_powergood input state

This bit shows the inversion of the gt_powergood input from the Versal adaptive SoC GT.

1 = gt_powergood not completed

0 = gt_powergood completed

5 Core Reset Register State

1 = tx/rx_reset asserted

0 = tx/rx_reset deasserted

4 Core External Reset Pin State

1 = tx/rx_core_reset asserted

0 = tx/rx_core_reset deasserted

1 1 0 Reset type

1= Initiates a Datapath only reset

0 = Initiates a PLL+ Datapath reset

Reset type should be asserted first followed by the reset bit 0.

0 0 Reset. (not self-clearing)

1 = put core into reset

0 = Release core from reset

After setting this bit to 1 and clearing back to 0, this bit will read back 1 until the reset process has completed.

  1. For Versal adaptive SoCs only.
Table 5. CTRL_ENABLE
Bits Default Value Description
1 0 Enable Data Interface.

1 = Enables the AXI4-Stream Data interface and transmits/receives data on the link.

0 = The link will be transmitting/receiving scrambled 0s

0 0 Enable Cmd interface.

1 = Enables the AXI4-Stream Cmd interface and the associated processing of the sync header meta data.

0 = Cmd words will be zeroed.

Table 6. CTRL_TX_SYNC
Bits Default Value Description
0 0 tx_sync_force.

Force on 8B10B transmitter. When set to 1, this register overrides the value on the tx_sync pin.

Table 7. CTRL_MB_IN_EMB
Bits Default Value Description
7:0 0x1 Number of multiblocks in an extended multiblock. Program this register with the actual value.
Note: 0 is not valid.
Table 8. CTRL_SUB_CLASS
Bits Default Value Description
1:0 0x1 Sub Class:

0 = Subclass 0

1 = Subclass 1

2 = Subclass 2 (8B10B only)

Table 9. CTRL_META_MODE
Bits Default Value Description
1:0 0x0 Meta Mode:

0 = CRC12

1 = N/A

2 = CMD

3 = FEC

Table 10. CTRL_8B10B_CFG
Bits Default Value Description
31:24 0x3 ILA multiframes. Multiframes in the Transmitted Initial Lane Alignment Sequence.

Parameter Range: 4–256; program the register with required value minus 1.

21:20 0x0 Reserved. Must be set to zero.
19 0 1 = Enable Link Error counters (Link errors are counted and reported using Link Error Count registers per lane)

0 = Disable Link Error counters

18 0 Error Reporting via sync:

1 = Error reporting using SYNC interface Enabled

0 = Error reporting using SYNC interface Disabled

17 1 ILA Required:

1 = Enable ILA Support

0 = Disable ILA Support

16 1 Scrambling:

1 = Enable Scrambling

0 = Disable Scrambling

12:8 0xF Frames per Multiframe (K)

Parameter range 1–32;

Program register with required value minus 1

(for example, for K = 16, 0x0F should be programmed)

7:0 0x1 Octets per Frame (F)

Parameter range 1–256;

Program register with required value minus 1

(for example, for F = 4, 0x03 should be programmed)

Table 11. CTRL_LANE_ENA
Bits Default Value Description
7:0 Lane enable register.

Default is all lanes enabled.

Set one bit per lane (bit 0 = lane 0, bit 1 = lane 1 etc.)

Note: If any lanes are disabled, the lane ID and the number of lanes per link registers should be reprogrammed accordingly.
Table 12. CTRL_RX_BUF_ADV
Bits Default Value Description
9:0 0x0 Advance the release of the receiver buffer:

For 64B66B linecoding, advance the release of the buffer by N 64 bit words. The range of N is between 0 and 31 words.

For 8B10B linecoding, advance the release of the buffer by N octets. The range of N is between 0 and 127 octets.

Table 13. CTRL_TEST_MODE
Bits Default Value Description
30:28 0x0 GT loopback: (TX only)

00: Normal operation

001: Near-End PCS Loopback

010: Near-End PMA Loopback

011: Reserved

100: Far-End PMA Loopback

101: Reserved

110: Far-End PCS Loopback

Note: The above bits maps directly to the GT loopback input ports. Refer to the specific GT user guide for more details.
27:12 Reserved
11:8 0x0 PRBS mode select (Versal adaptive SoCs only):

4'b0000: Standard operation mode. (PRBS off)

4'b0001: PRBS-7

4'b0010: PRBS-9

4'b0011: PRBS-15

4'b0100: PRBS-23

4'b0101: PRBS-31

4'b0110: PRBS-13

2:0 0x0 Test mode select (8B10B mode):

000 = Normal operation

001 = Transmit receive /K28.5/ indefinitely 2

010 = Synchronize as normal then transmit/receive repeated ILA sequences. 2

101 = Transmit Modified Random Pattern RPAT (TX only) 1

111 = Transmit Scrambled Jitter Pattern JSPAT (TX only) 1

  1. These test modes are only applicable to the JESD204C 8B10B transmitter IP. They are used to set the transceiver to output specific patterns that might be used to evaluate the electrical characteristics of a link using tools such as IBERT. A JESD204 8B10B receiver core will not synchronize or function if these test patterns are received.
  2. Physical layer test modes are made available through the Versal Adaptive SoC Transceiver or JESD204 PHY register interface.
Table 14. CTRL_RX_MBLOCK_TH
Bits Default Value Description
2:0 0x0 MB lock threshold.

How many correct/incorrect multiblock alignment markers are required to achieve/lose multiblock lock. The actual value used is 1 plus the number in this register.

Table 15. CTRL_SYSREF
Bits Default Value Description
23:16 0x0 (For 64b66b cores only)

SYSREF Delay:

Add additional delay to SYSREF alignment LEMC.

0xFF = 255 core_clk cycles delay

....

0x00 = 0 core_clk cycles delay.

This register is used to retard the phase of the LEMC.

19:16 0x0 SYSREF Delay:

Add additional delay to SYSREF alignment of LMFC.

1111 = 15 core_clk cycles delay

....

0000 = 0 core_clk cycles delay

This register is used to retard the phase of the LMFC.

10:8 0x0 SYSREF Tolerance:

Specify a tolerance value in core_clk cycles for SYSREF detection when in SYSREF Always mode. If a SYSREF event is detected within +/- tolerance core_clk cycles from its expected position, no error signal will be issued.

1 0 SYSREF Required on Re-Sync

1 = Following a Link Re-Sync event, a SYSREF event is required to re-align the local LMFC/LEMC before the link will operate.

0 = No SYSREF is required to restart a link after a Re-sync event.

0 0 SYSREF Always

1 = The core will align the LMFC/LEMC counter on all SYSREF events.

0 = The core will only align the LMFC/LEMC counter on the first SYSREF event following a reset, all subsequent SYSREF events will be ignored.

Table 16. STAT_LOCK_DEBUG
Bits Default Value Description
23:16 Lane indicator multiblock aligned.

1 bit per lane.

Set to 1 when multiblock alignment is achieved. 0 otherwise.

7:0 Lane indicator 64B66B sync header aligned.

1 bit per lane.

Set to 1 when sync header alignment is achieved. 0 otherwise.

Table 17. STAT_RX_ERR
Bits Default Value Description
31:28 RX Error status lane 7
27:24 RX Error status lane 6
23:20 RX Error status lane 5
19:16 RX Error status lane 4
15:12 RX Error status lane 3
11:8 RX Error status lane 2
7:4 RX Error status lane 1
3:0 RX Error status lane 0

Bit 3: unused

Bit 2: Unexpected K-character(s) received

Bit 1: Disparity Error(s) received

Bit 0: Not in table Error(s) received

Each bit indicates that 1 or more errors of that type have been received in Lane 0 because the register was last read.

All status bits are cleared to 0 on read of this register.

Table 18. STAT_RX_DEBUG
Bits Default Value Description
31:28 Link Debug status Lane 7 as per lane 0
27:24 Link Debug status Lane 6 as per lane 0
23:20 Link Debug status Lane 5 as per lane 0
19:16 Link Debug status Lane 4 as per lane 0
15:12 Link Debug status Lane 3 as per lane 0
11:8 Link Debug status Lane 2 as per lane 0
7:4 Link Debug status Lane 1 as per lane 0
3:0 Link Debug status Lane 0

Bit 3: 1 = Start of Data was Detected 1

Bit 2: 1 = Start of ILA was Detected 1

Bit 1: 1 = Lane has Code Group Sync 2

Bit 0: 1 = Lane is currently receiving K28.5's (BC alignment characters) 2

  1. The status bits 3:2 latch when set and are cleared on read or when the core is reset. If the core is streaming data when these bits are cleared, they are instantly set again. The purpose of these bits is to detect whether these conditions have occurred because SYNC was asserted.
  2. The status bits 1:0 show instantaneous status.
Table 19. STAT_STATUS
Bits Default Value Description
15 8B10B Alignment Error:

1= An 8B10B RX misalignment has been detected. Misalignment is determined by monitoring the Multiframe framing characters. If eight consecutive framing characters are detected in misaligned positions, then this bit is asserted.

14 8B10B RX started:

1 = The link has started outputting data on the AXI4-Stream port. This bit is applicable to an 8B10B RX only.

13 8B10B CGS status:

1 = The link has achieved Code Group Sync. This bit is applicable to an 8B10B RX only.

12 8B10B SYNC status:

1 = The receiver has signaled SYNC has been achieved. This bit is applicable to an 8B10B link only.

10 Buffer Overflow error.

1 = The receiver buffer has overflowed.

5 64B66B Multiblock Lock Status:

1 = Multiblock lock achieved on all lanes

This bit is a logical AND of the individual lane status bits.

4 64B66B Sync Header Lock Status:

1 = Sync Header lock achieved on all lanes.

This bit is a logical AND of the individual lane status bits

2 SYSREF error. A sysref was detected out of phase with the local extended multiblock clock.
1 SYSREF captured.
0 Interrupt pending.
Table 20. CTRL_IRQ
Bits Default Value Description
14 0 1 = Enable interrupt on 8B10B RX AXI4-Stream data start.
13 0 1 = Enable interrupt on 8B10B RX Resync request.
12 0 1 = Enable interrupt on 8B10B SYNC assertion.
10 0 1 = Enable Interrupt on overflow Error.
9 0 1 = Enable Interrupt on 64B66B FEC Error.
8 0 1 = Enable Interrupt on 64B66B CRC Error.
7 0 1 = Enable Interrupt on 64B66B Multiblock Error.
6 0 1 = Enable Interrupt on 64B66B Block Sync Error.
5 0 1 = Enable Interrupt on Loss of 64B66B Multiblock Lock.
4 0 1 = Enable Interrupt on Loss of 64B66B Sync Header Lock.
2 0 1 = Enable Interrupt on SYSREF Error.
1 0 1 = Enable Interrupt on SYSREF Received.
0 0 Global Interrupt Enable:

Must be set for any interrupt to function.

Table 21. STAT_IRQ
Bits Default Value Description
14 1 = 8B10B RX AXI4-Stream data start interrupt triggered.
13 1 = 8B10B RX Resync request interrupt triggered.
12 1 = 8B10B SYNC assertion interrupt triggered.
10 1 = Overflow Error Interrupt triggered.
9 1 = 64B66B FEC Error detected Interrupt triggered.
8 1 = 64B66B CRC Error detected Interrupt triggered.
7 1 = 64B66B Multiblock Error detected Interrupt triggered.
6 1 = 64B66B Block Sync Error detected Interrupt triggered.
5 1 = 64B66B Multiblock Lock Status Interrupt triggered.
4 1 = 64B66B Sync Header Lock Status Interrupt triggered.
2 1 = SYSREF Error Interrupt triggered.
1 1 = SYSREF Received Interrupt triggered.
Table 22. CTRL_TX_ILA_CFG0
Bits Default Value Description
11:8 0x0 BID (Bank ID). Binary value.
7:0 0x0 DID (Device ID). Binary value.
Table 23. CTRL_TX_ILA_CFG1
Bits Default Value Description
31:26 Reserved
25:24 0x0 CS (Control bits per Sample). Binary value.
23:21 Reserved
20:16 0x0 N' (Totals bits per Sample). Binary value minus 1.
15:13 Reserved
12:8 0x0 N (Converter Resolution). Binary value minus 1.
7:0 0x0 M (Converters per Device). Binary value minus 1.
Table 24. CTRL_TX_ILA_CFG2
Bits Default Value Description
28:24 0x0 CF (Control Words per Frame). Binary value.
16 0 HD (High Density format)
12:8 0x0 S (Samples per Converter per Frame). Binary value minus 1.
Table 25. CTRL_TX_ILA_CFG3
Bits Default Value Description
31:17 Reserved
16 0 ADJDIR (Adjust Direction) [Subclass 2 Only]. Binary value.
15:9 Reserved
8 0 PHADJ (Phase Adjust Request) [Subclass 2 Only]. Binary value.
7:4 Reserved
3:0 0x0 ADJCNT (Phase Adjust Count) [Subclass 2 Only]. Binary value.

RX: captured configuration data from the ILA sequence (per lane).

TX: Sets the values to be transmitted in the ILA sequence for all lanes.

Table 26. CTRL_TX_ILA_CFG4
Bits Default Value Description
15:8 0x0 RES2 (Reserved Field 2)
7:0 0x0 RES1 (Reserved Field 1)
Table 27. STAT_RX_BUF_LVL
Bits Default Value Description
9:0 Buffer fill level.

The amount of data in the receiver buffer for lane 0.

For 64B66B linecoding: The value returned is the number of 64-bit words in the buffer.

For 8B10B Linecoding: The value returned is the number of bytes in the buffer.

  1. This is a Per Lane Register
Table 28. CTRL_TX_ILA_LID
Bits Default Value Description
31:21 Reserved
20:16 L Number of lanes per link (binary value minus 1).

The default value for all lanes is L (total number of lanes minus 1). These values should be programmed when:

  • Not all lanes in the generated IP core are enabled.
  • A single TX core is used to drive multiple DAC devices.
  • Multiple TX cores are combined to create links with more than eight lanes.
15:5 Reserved
4:0 N ID of lane N. Value can be anywhere between 0 and 31. The default value N is set to the lane number. For interfaces using more than 8 lanes and hence multiple JESD204 cores, this register should be programmed to ensure each lane has the correct identifier.
  1. This is a Per Lane Register
Table 29. STAT_RX_ERROR_CNT0
Bits Default Value Description
31:16 CRC error counter.
15:8 64B66B Multiblock alignment error counter.
7:0 64B66B Sync Header alignment error counter.
  1. This is a Per Lane Register. The counts are cumulative and are cleared on read or reset. The counts should be cleared with a register read when a link has been successfully established.
Table 30. STAT_RX_ERROR_CNT1
Bits Default Value Description
31:16 64B66B FEC uncorrected errors counter.
15:0 64B66B FEC corrected errors counter.
  1. This is a Per Lane Register. The counts are cumulative and are cleared on read or reset. The counts should be cleared with a register read when a link has been successfully established.
Table 31. STAT_LINK_ERR_CNT
Bits Default Value Description
31:0 Link Error Count

Count of total received link errors (per lane) when Link Error Counters is Enabled.

Errors counted are Disparity or Not In Table errors indicated by the lane.

The error counter can be reset by disabling and re-enabling the Link Error Counters Enable, bit 19 in the CTRL_8B10B_CFG register.

  1. This is a Per Lane Register.
Table 32. STAT_TEST_ERR_CNT
Bits Default Value Description
31:0 Test Mode Error Count

Count of Errors received in Data link Layer test modes.

Test Mode = 001 (Continuous K28.5): counts any non K28.5 characters received

Test Mode = 010 (Continuous ILA): counts any unexpected characters received

This count resets to zero on transition to an active test mode and retains any count value on transition out of an active test mode.

  1. This is a Per Lane Register.
Table 33. STAT_TEST_ILA_CNT
Bits Default Value Description

31:0

Test Mode ILA Count

Count of total ILA Sequences received when Test Mode = 010 (Continuous ILA)

This count resets to zero on transition to Test Mode = 010, and retains any count value on transition out of test mode.

  1. This is a Per Lane Register.
Table 34. STAT_TEST_MF_CNT
Bits Default Value Description
31:0 Test Mode Multiframe Count

Count of total ILA Multiframes received when Test Mode = 010 (Continuous ILA)

This count resets to zero on transition to Test Mode = 010 and retains any count value on transition out of test mode.

  1. This is a Per Lane Register.
Table 35. CTRL_RX_ILA_CFG0
Bits Default Value Description
31:11 Reserved
10:8 JESDV (JESD204 version):

000=JESD204A

001=JESD204B

010 = JESD204C

7:3 Reserved
2:0 SUBCLASS:

000=Subclass0

001=Subclass1

010=Subclass2

  1. This is a Per Lane Register.
Table 36. CTRL_RX_ILA_CFG1
Bits Default Value Description
31:8 Reserved
7:0 F (Octets per Frame). Binary value minus 1.
  1. This is a Per Lane Register.
Table 37. CTRL_RX_ILA_CFG2
Bits Default Value Description
31:5 Reserved
4:0 K (Frames per Multiframe). Binary value minus 1.
  1. This is a Per Lane Register.
Table 38. CTRL_RX_ILA_CFG3
Bits Default Value Description
31:29 Reserved
28:24 L (Lanes per Link). Binary value minus 1.
23:21 Reserved
20:16 0x0 LID (Lane ID). Binary value.
15:12 Reserved
11:8 0x0 BID (Bank ID). Binary value.
7:0 0x0 DID (Device ID). Binary value.
  1. This is a Per Lane Register.
Table 39. CTRL_RX_ILA_CFG4
Bits Default Value Description
31:26 Reserved
25:24 (Control bits per Sample). Binary value.
23:21 Reserved
20:16 N' (Totals bits per Sample). Binary value minus 1.
15:13 Reserved
12:8 N (Converter Resolution). Binary value minus 1.
7:0 M (Converters per Device). Binary value minus 1.
  1. This is a Per Lane Register.
Table 40. CTRL_RX_ILA_CFG5
Bits Default Value Description
31:29 Reserved
28:24 0x0 CF (Control Words per Frame). Binary value.
23:17 Reserved
16 0 HD (High Density format)
15:13 Reserved
12:8 0x0 S (Samples per Converter per Frame). Binary value minus 1.
0 SCR (Scrambling Enable) [RX only, not writeable for TX]

1 = enabled

  1. This is a Per Lane Register.
Table 41. CTRL_RX_ILA_CFG6
Bits Default Value Description
31:17 Reserved
16 0 ADJDIR (Adjust Direction) [Subclass 2 Only]. Binary value.
15:9 Reserved
8 PHADJ (Phase Adjust Request) [Subclass 2 Only]. Binary value.
7:4 Reserved
3:0 0x0 ADJCNT (Phase Adjust Count) [Subclass 2 Only]. Binary value.

RX: captured configuration data from the ILA sequence (per lane).

TX: Sets the values to be transmitted in the ILA sequence for all lanes.

  1. This is a Per Lane Register.
Table 42. CTRL_RX_ILA_CFG7
Bits Default Value Description
31:24 Reserved
23:16 0x0 FCHK (Checksum) [RX only, not writeable for TX]. Binary value.
15:8 0x0 RES2 (Reserved Field 2)
7:0 0x0 RES1 (Reserved Field 1)
  1. This is a Per Lane Register.
Table 43. CTRL_TX_GT
Bits Default Value Description
31:5 Reserved
4 0 TXINHIBIT

Set High to inhibit transmission of TX data

3 0 TXELECIDLE

Set High to force idle signal on transmitter output

2:1 0x0 TXPD

TX power down

0 0 TXPOLARITY

Set High to invert the polarity of the outgoing TX data

  1. This is a Per Lane Register for Versal adaptive SoCs only.
Table 44. CTRL_RX_GT
Bits Default Value Description
31:3 Reserved
2:1 0x0 RXPD

RX power down

0 0 RXPOLARITY

Set High to invert the polarity of the incoming RX data.

  1. This is a Per Lane Register for Versal adaptive SoCs only.
Table 45. CTRL TX VERSAL GTY/GTYP
Bits Default Value Description
31:15 Reserved
14:10 0x0 TXPOSTCURSOR

Transmitter post-cursor pre-emphasis control

9:5 0x0 TXPRECURSOR

Transmitter pre-cursor pre-emphasis control

4:0 0x18 TXDIFFCTRL

Driver swing control

  1. This is a Per Lane Register for GTY/GTYP Versal adaptive SoCs only.
Table 46. CTRL TX VERSAL GTM
Bits Default Value Description
31 Reserved
30:25 0x0 TXPOSTCURSOR

Transmitter post-cursor pre-emphasis control

24:19 0x0 TXPRECURSOR3

Transmitter pre-cursor3 pre-emphasis control

18:13 0x0 TXPRECURSOR2

Transmitter pre-cursor2 pre-emphasis control

12:7 0x0 TXPRECURSOR

Transmitter pre-cursor pre-emphasis control

6:0 0x0 TXMAINCURSOR

Driver swing control

  1. This is a Per Lane Register for GTM Versal adaptive SoCs only.