Register Space - 4.2 English

0=FEC not included

(FEC is only available when configured for 64B66B)

0 = Core is 8B10B

0 = Core is RX

1-bit per enabled GT lane. These bits show the inversion of the mstresetdone inputs from the Versal adaptive SoC GTs.

1-bit per enabled GT lane. These bits show the inversion of the pmaresetdone inputs from the Versal adaptive SoC GTs.

1 = GTs are still in reset

0 = GTs have finished reset

This bit shows the inversion of the gt_powergood input from the Versal adaptive SoC GT.

1 = gt_powergood not completed

0 = gt_powergood completed

1 = tx/rx_reset asserted

0 = tx/rx_reset deasserted

1 = tx/rx_core_reset asserted

0 = tx/rx_core_reset deasserted

1= Initiates a Datapath only reset

0 = Initiates a PLL+ Datapath reset

Reset type should be asserted first followed by the reset bit 0.

1 = put core into reset

0 = Release core from reset

After setting this bit to 1 and clearing back to 0, this bit will read back 1 until the reset process has completed.

1 = Enables the AXI4-Stream Data interface and transmits/receives data on the link.

0 = The link will be transmitting/receiving scrambled 0s

1 = Enables the AXI4-Stream Cmd interface and the associated processing of the sync header meta data.

0 = Cmd words will be zeroed.

Force on 8B10B transmitter. When set to 1, this register overrides the value on the tx_sync pin.

0 = Subclass 0

1 = Subclass 1

2 = Subclass 2 (8B10B only)

0 = CRC12

1 = N/A

2 = CMD

3 = FEC

Parameter Range: 4–256; program the register with required value minus 1.

0 = Disable Link Error counters

1 = Error reporting using SYNC interface Enabled

0 = Error reporting using SYNC interface Disabled

1 = Enable ILA Support

0 = Disable ILA Support

1 = Enable Scrambling

0 = Disable Scrambling

Parameter range 1–32;

Program register with required value minus 1

(for example, for K = 16, 0x0F should be programmed)

Parameter range 1–256;

Program register with required value minus 1

(for example, for F = 4, 0x03 should be programmed)

Default is all lanes enabled.

Set one bit per lane (bit 0 = lane 0, bit 1 = lane 1 etc.)

For 64B66B linecoding, advance the release of the buffer by N 64 bit words. The range of N is between 0 and 31 words.

For 8B10B linecoding, advance the release of the buffer by N octets. The range of N is between 0 and 127 octets.

00: Normal operation

001: Near-End PCS Loopback

010: Near-End PMA Loopback

011: Reserved

100: Far-End PMA Loopback

101: Reserved

110: Far-End PCS Loopback

4'b0000: Standard operation mode. (PRBS off)

4'b0001: PRBS-7

4'b0010: PRBS-9

4'b0011: PRBS-15

4'b0100: PRBS-23

4'b0101: PRBS-31

4'b0110: PRBS-13

000 = Normal operation

001 = Transmit receive /K28.5/ indefinitely ²

010 = Synchronize as normal then transmit/receive repeated ILA sequences. ²

101 = Transmit Modified Random Pattern RPAT (TX only) ¹

111 = Transmit Scrambled Jitter Pattern JSPAT (TX only) ¹

How many correct/incorrect multiblock alignment markers are required to achieve/lose multiblock lock. The actual value used is 1 plus the number in this register.

SYSREF Delay:

Add additional delay to SYSREF alignment LEMC.

0xFF = 255 core_clk cycles delay

....

0x00 = 0 core_clk cycles delay.

This register is used to retard the phase of the LEMC.

Add additional delay to SYSREF alignment of LMFC.

1111 = 15 core_clk cycles delay

....

0000 = 0 core_clk cycles delay

This register is used to retard the phase of the LMFC.

Specify a tolerance value in core_clk cycles for SYSREF detection when in SYSREF Always mode. If a SYSREF event is detected within +/- tolerance core_clk cycles from its expected position, no error signal will be issued.

1 = Following a Link Re-Sync event, a SYSREF event is required to re-align the local LMFC/LEMC before the link will operate.

0 = No SYSREF is required to restart a link after a Re-sync event.

1 = The core will align the LMFC/LEMC counter on all SYSREF events.

0 = The core will only align the LMFC/LEMC counter on the first SYSREF event following a reset, all subsequent SYSREF events will be ignored.

1 bit per lane.

Set to 1 when multiblock alignment is achieved. 0 otherwise.

1 bit per lane.

Set to 1 when sync header alignment is achieved. 0 otherwise.

Bit 3: unused

Bit 2: Unexpected K-character(s) received

Bit 1: Disparity Error(s) received

Bit 0: Not in table Error(s) received

Each bit indicates that 1 or more errors of that type have been received in Lane 0 because the register was last read.

All status bits are cleared to 0 on read of this register.

Bit 3: 1 = Start of Data was Detected ¹

Bit 2: 1 = Start of ILA was Detected ¹

Bit 1: 1 = Lane has Code Group Sync ²

Bit 0: 1 = Lane is currently receiving K28.5's (BC alignment characters) ²

1= An 8B10B RX misalignment has been detected. Misalignment is determined by monitoring the Multiframe framing characters. If eight consecutive framing characters are detected in misaligned positions, then this bit is asserted.

1 = The link has started outputting data on the AXI4-Stream port. This bit is applicable to an 8B10B RX only.

1 = The link has achieved Code Group Sync. This bit is applicable to an 8B10B RX only.

1 = The receiver has signaled SYNC has been achieved. This bit is applicable to an 8B10B link only.

1 = The receiver buffer has overflowed.

1 = Multiblock lock achieved on all lanes

This bit is a logical AND of the individual lane status bits.

1 = Sync Header lock achieved on all lanes.

This bit is a logical AND of the individual lane status bits

Must be set for any interrupt to function.

RX: captured configuration data from the ILA sequence (per lane).

TX: Sets the values to be transmitted in the ILA sequence for all lanes.

The amount of data in the receiver buffer for lane 0.

For 64B66B linecoding: The value returned is the number of 64-bit words in the buffer.

For 8B10B Linecoding: The value returned is the number of bytes in the buffer.

The default value for all lanes is L (total number of lanes minus 1). These values should be programmed when:

• Not all lanes in the generated IP core are enabled.
• A single TX core is used to drive multiple DAC devices.
• Multiple TX cores are combined to create links with more than eight lanes.

Count of total received link errors (per lane) when Link Error Counters is Enabled.

Errors counted are Disparity or Not In Table errors indicated by the lane.

The error counter can be reset by disabling and re-enabling the Link Error Counters Enable, bit 19 in the CTRL_8B10B_CFG register.

Count of Errors received in Data link Layer test modes.

Test Mode = 001 (Continuous K28.5): counts any non K28.5 characters received

Test Mode = 010 (Continuous ILA): counts any unexpected characters received

This count resets to zero on transition to an active test mode and retains any count value on transition out of an active test mode.

31:0

Count of total ILA Sequences received when Test Mode = 010 (Continuous ILA)

This count resets to zero on transition to Test Mode = 010, and retains any count value on transition out of test mode.

Count of total ILA Multiframes received when Test Mode = 010 (Continuous ILA)

This count resets to zero on transition to Test Mode = 010 and retains any count value on transition out of test mode.

000=JESD204A

001=JESD204B

010 = JESD204C

000=Subclass0

001=Subclass1

010=Subclass2

1 = enabled

RX: captured configuration data from the ILA sequence (per lane).

TX: Sets the values to be transmitted in the ILA sequence for all lanes.

Set High to inhibit transmission of TX data

Set High to force idle signal on transmitter output

TX power down

Set High to invert the polarity of the outgoing TX data

RX power down

Set High to invert the polarity of the incoming RX data.