In AMD Versal™ adaptive SoCs, the GTY, GTYP, and GTM serial transceivers require a stable, low-jitter reference clock which has a device and speed grade-dependent range. For AMD UltraScale+™ and AMD UltraScale™ devices, the GTH/GTY serial transceivers in the JESD204_PHY require a stable, low-jitter reference clock which has a device and speed grade-dependent range.
In some circumstances, it can be advantageous to use the same clock frequency for both core clock and reference clock. However, this might not always be practical. It is important to understand the limitations imposed on the reference clock and core clock, together with system-level implications such as the synchronous capture of SYSREF for Subclass 1.