Lane alignment is achieved using 64B66B encoding in the following manner.
Each lane has a receiver buffer, which is two multiblocks deep, 2 x 32 64-bit words.
Each lane’s receive buffer starts buffering data when the EOEMB is received. When the last arriving lane has received its EOEMB, all lane receive buffers are released on the next LEMC, so that all lanes are aligned and released at the right time.
For designs where EMB > 2 MB, extra care should be taken to ensure the buffer does not overflow. The following figure shows an example where E = 3, i.e., there are three multiblocks in an EMB. The figure shows before and after an adjustment to the SYSREF_DELAY register has been made. In the before case, the LEMC boundaries straddle the receive buffer, so it is not released and the buffer overflows. In the after case, the LEMC boundary has been shifted by N clock cycles to place it in the safe TW allowing the buffer to be released correctly with no overflow.