Receive Latency - 4.2 English

JESD204C LogiCORE IP Product Guide (PG242)
Document ID
PG242
Release Date
2023-11-06
Version
4.2 English

The latency variation is critical for JESD204C systems. The receive latency through the IP core is fixed, although it can be varied under user control—see Minimum Deterministic Latency Support for details, but the transceiver introduces some variation as the internal receive elastic buffer of the transceiver is included in the data path. The variation in latency is compensated automatically by the core to ensure that the overall end-to-end latency has no variation. Refer to the Latency calculations checklist (AR: 66143).

The 8B10B and 64B66B receive data path latencies are shown in the following tables. They do not include the latency through the JESD204_PHY IP core if using UltraScale/UltraScale+, or the GT Quad if using a Versal adaptive SoC (GTdelay).

If using UltraScale or UltraScale+, the receive latency through the JESD204_PHY IP core is equal to the latency through the GT (GTdelay). There is no additional latency added by the JESD204_PHY IP core. Refer to the relevant GT for the PHY latency values.

Table 1. 8B10B Receive Data Path Latency Through JESD204C
  GTME5 Transceiver All Other Transceivers
TRXLMFC (octet clks) 32 16
TRXIN TRXLMFC + GTdelay TRXLMFC + GTdelay
TRXOUT 0 0
  1. Latency values are given in 8b10b octet clocks. See RX End to End Latency for detailed use.
  2. When using Versal adaptive SoC GTME5 transceivers, there is an additional latency in the receive data path because the 8b10b decoding function is performed external to the GT Quad.
Table 2. 64B66 Receive Data Path Latency Through JESD204C
  GTME5 Transceiver All Other Transceivers
  With FEC Without FEC With FEC Without FEC
TRXLEMC (core clks) 17 +/-1 15 +/-1 8 6
TRXIN TRXLMFC + GTdelay TRXLMFC + GTdelay TRXLMFC + GTdelay TRXLMFC + GTdelay
TRXOUT 0 0 0 0
  1. Latency values are given in core clocks. See RX End to End Latency for detailed use.
  2. When using Versal adaptive SoC GTME5 transceivers, there is an additional latency through the receive data path because the 64b66b decoding function is performed external to the GT Quad.
  3. When using Versal adaptive SoC GTME5 transceivers, there is an additional +/-1 clock cycle of uncertainty due to the clock crossing from the rxusrclk to the rx_core_clk within the 64b66b decoder gearbox.