RX Core - 4.2 English

Table 1. RX Core: System Signals
Signal Name	Interface	I/O	Description
rx_core_clk	System s_axis_rx s_axis_rx_cmd	I	Core logic clock input. Frequency: Serial line rate / 66 (for 64B66B linecoding) Serial line rate / 40 (for 8B10B linecoding)
rx_core_reset	System	I	Core asynchronous logic reset active-High.
rx_aresetn	s_axis_rx s_axis_rx_cmd	O	AXI4-Stream interface reset. Active-Low. Associated with both data and command interfaces.
s_axi_aclk	s_axi	I	AXI4-Lite clock input.
s_axi_aresetn	s_axi	I	AXI4-Lite reset input. Active-Low.
s_axi*	s_axi	I	See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for a description of AXI4 signals.
irq	System	O	System interrupt output.
rx_sysref	System	I	SYSREF input. When Subclass 1 mode is selected, this signal is required and used by the core to set the phase of the local extended multi-block clock. This SYSREF signal must be generated synchronous to the core clock. This input should be driven from an external device generating SYSREF for both TX and RX on a link.
rx_sync	System	O	Sync signal. The sync signal is defined as an active-Low sync request signal by JESD204, so this signal is Low until comma alignment is completed and High to indicate the receiver is ready for ILA and normal data. This signal is only available when the core is generated with 8B10B linecoding selected.
encommaalign	System	O	Enable/disable 8B10B comma alignment logic within the JESD204_PHY or the Versal adaptive SoC (excluding GTM). Transceiver GT Quad: this port should be connected to the Versal adaptive SoC GT Quad as follows: JESD Channel 0: GPI[8] JESD Channel 1: GPI[9] JESD Channel 2: GPI[10] JESD Channel 3: GPI[11] This signal is only available when the core is generated with 8B10B linecoding selected and is N/A for Versal adaptive SoC GTM designs.
Versal Adaptive SoCs
gt_powergood¹	System	I	This active-High signal from Versal Adaptive SoC Transceiver indicates when the GT clocking resources have completed power up.
rxusrclk¹	System	I	Versal Adaptive SoC GTM 66-bit clock used for 64b66b decoder gearbox (GTM only).
UltraScale+/UltraScale Devices
rx_reset_gt	System	O	JESD204_PHY RX datapath reset. Core output to reset the receive datapath in a connected JESD204_PHY. This must be connected to a JESD204_PHY.
rx_reset_done	System	I	JESD204_PHY RX reset done input. Indicates the JESD204_PHY has completed the receive reset process. For an example of how to connect this port to the JESD204_PHY or Versal adaptive SoC GT Quad, generate the example design.
For an example of how to connect this port to the Versal adaptive SoC GT Quad, generate the example design.

Table 2. RX Core: Versal Adaptive SoC GT RX Interface Ports
Signal Name	Interface	I/O	Description
chN_rxctrl0[15:0]	GT_RX	I	RX Char is K from the Versal Adaptive SoC Transceiver. N = Lanes -1
chN_rxctrl1[15:0]	GT_RX	I	RX Disparity Error from the Versal Adaptive SoC Transceiver. N = Lanes -1
chN_rxctrl2[7:0]	GT_RX	I	RX Char is Comma from the Versal Adaptive SoC Transceiver. N = Lanes -1
chN_rxctrl3[7:0]	GT_RX	I	RX Not In Table Error from the Versal Adaptive SoC Transceiver. N = Lanes -1
chN_rxdata[127:0] ³	GT_RX	I	RX Data from the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxdatavalid[1:0]	GT_RX	I	RX Data Valid from the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxgearboxslip	GT_RX	O	RX Gearbox Slip to the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxheader[5:0]	GT_RX	I	RX Header from the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxheadervalid[1:0]	GT_RX	I	RX Header Valid from the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxlpmen	GT_RX	O	RX LPM Mode Enable to the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxmstdatapathreset	GT_RX	O	RX Master Datapath only Reset sequence start to the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxmstreset	GT_RX	O	RX Master Reset sequence start to the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxmstresetdone	GT_RX	I	RX Master Reset sequence Done to the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxpd[1:0]	GT_RX	O	RX Power Down to the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxpmaresetdone	GT_RX	I	RX PMA Reset Done from the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxpolarity	GT_RX	O	RX Polarity control to the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxprbscntreset	GT_RX	O	RX PRBS Error Count Reset to the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxprbserr	GT_RX	I	RX PRBS Error from the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxprbslocked	GT_RX	I	RX PRBS Locked from the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxprbssel[3:0]	GT_RX	O	RX PRBS Select to the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxrate[7:0]	GT_RX	O	RX Line Rate Control to the Versal Adaptive SoC Transceiver. N = Lanes - 1
chN_rxuserrdy	GT_RX	O	RX User clocks stable to the Versal Adaptive SoC Transceiver. N = Lanes - 1
JESD204C only uses the above subset of the available signals on the Versal Adaptive SoC Transceiver Rx_GT_IP_Interface. For further details, see Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331). The signals in this table are connected between the JESD204C core and the Versal Adaptive SoC Transceiver using Block Automation, see Design Flow Steps for details. In Versal Adaptive SoC GTM designs this port is [255:0].

Table 3. RX Core: JESD204_PHY Interface Ports for UltraScale+/UltraScaleDevices
Signal Name	Interface	I/O	Description
gtN_rxdata[63:0]	PHY	I	RX data from JESD204 PHY. N = Lanes - 1
gtN_rxheader[1:0]	PHY	I	RX header from JESD204 PHY. N = Lanes - 1
gtN_misalign	PHY	I	Signal from JESD204 PHY to indicate a misaligned sync header was detected. N = Lanes - 1
gtN_block_sync	PHY	I	Signal from JESD204 PHY to indicate block sync status. N = Lanes -1
gtN_rxcharisk[3:0]	PHY	I	RX Char is K from JESD204 PHY. N = Lanes -1
gtN_rxdisperr[3:0]	PHY	I	RX Disparity Error from JESD204 PHY. N = Lanes -1
gtN_notintable[3:0]	PHY		RX Not In Table Error from JESD204 PHY. N = Lanes -1

Table 4. RX Core: Receive Interface (64B66B Linecoding Only)
Signal Name	Interface	I/O	Description
rx_tdata [(64*N)-1:0]	m_axis_rx	O	Receive data output. N = Lanes
rx_tvalid	m_axis_rx	O	AXI4-Stream tvalid.
rx_soemb	m_axis_rx	O	Start of extended multi-block boundary indication. Set to 1 to indicate tx_tdata in the following clock cycle is the start of an extended multi-block.
rx_emb_err	m_axis_rx	O	Extended Multi-block Error. Set to 1 on the last block of an extended multi-block if a multi-block alignment error was detected.
rx_crc_err	m_axis_rx	O	CRC error. Set to 1 on the last block of an multi-block if a CRC or Uncorrectable FEC error was detected within the multi-block.
rx_cmd_tdata[(32*N)-1:0]	m_axis_rx_cmd	O	Transmit Cmd interface. N = Lanes For Meta mode = CRC, Cmd payload is bits [6:0] with bits [31:7] set to Zero. For Meta mode = CMD, Cmd payload is [18:0] with bits [31:19] set to Zero
rx_cmd_tvalid	m_axis_rx_cmd	O	AXI4-Stream tvalid. rx_cmd_tvalid will be set for one cycle every multi-block to control the Cmd word flow.
rx_cmd_tready	m_axis_rx_cmd	I	AXI4-Stream tready.
rx_cmd_tuser[N:0]	m_axis_rx_cmd	O	AXI4-Stream tuser. N = Lanes - 1. The tuser data bits are used to signal that a Multiblock Alignment error was detected in the previous multiblock of the associated lane. This might mean the CMD data is invalid.

Table 5. RX Core: Receive Interface (8B10B Linecoding Only)
Signal Name	Interface	I/O	Description
rx_tdata [(32*N)-1:0]	m_axis_rx	O	Receive data output. N = Lanes
rx_tvalid	m_axis_rx	O	AXI4-Stream tvalid.
rx_sof[3:0]	m_axis_rx	O	Start of frame boundary indication. The position of the first byte in a frame is encoded in the same way as tx_sof [3:0]. This signal is asserted one cycle before the AXI4-Stream data. The alignment of the first valid byte is always in byte 0 if the multiframe size is a multiple of 4 and rx_buffer_delay is a multiple of 4.
rx_somf[3:0]	m_axis_rx	O	Start of multiframe boundary indication. The position of the first byte of each multiframe is encoded in the same way as rx_sof.
rx_frm_err[3:0]	m_axis_rx	O	Error in byte. JESD204 specifies that data must be replicated from the previous frame if certain errors occur. The core does not buffer the previous frame. You can choose to implement a frame buffer or use a buffer elsewhere in the system to perform this function if required. The rx_frm_err signal indicates that a single byte error exists in the data stream. There is one bit for each byte of each AXI4-Stream. For example, a four lane interface has four 32-bit AXI4-Streams, the error signal is 16 bits wide with bit 15 of the error signal corresponding to the most significant byte of lane 4 and bit 0 of the error signal corresponding to the least significant byte of lane 1. This signal is synchronous to rx_core_clk and output in the cycle before the data in the same way as rx_sof.