Run time operation of the JESD204C core is configured through an AXI4-Lite register interface. See Register Space for details of the register map and available configuration registers.
For correct operation and bring-up of a JESD204C link, it is important that the major framing and link operation parameters match at both ends of the link. These parameters are determined by the configurations available in the ADC/DAC converter device to which the core is interfacing.
For 64B66B Linecoding, these are:
- Meta Mode
- Multiblocks in Extended Multiblock
- Subclass mode
- SYSREF handling (for subclass 1 mode)
For 8B10B Linecoding, these are:
- Octets per frame
- Frames per Multiframe
- Scrambling On/Off
- Subclass mode
- SYSREF handling (for subclass 1 mode)
For 8B10B transmitter cores, in addition to the above parameters, some of the additional content of the configuration data which is transmitted in the ILA sequence at link start-up is also programmed through the register interface. The data values transmitted in the ILA configuration data are not normally critical to the operation of the link, but this is dependent on the behavior of the receiving device.
For 8B10B receive cores, the configuration data received in the ILA sequence is captured for each lane and can be examined using the register interface.
After programming the link parameters, the JESD204C core must be reset to restart the link using the newly programmed values. If the JESD204C core is not reset after programming, the new parameters will not be used.