- Calculate the TW max and min values in words based on the receive buffer size
as follows.
TW Max = 64-2 = 62. (In the case where EMB=1, TW Max is not applicable)
TW Min = 0+2 = 2. (two CORE_CLK cycles)
- Configure the system and start the link. At this point, all delays can be unknown.
- Once the link is running, read the JESD204C 64B66B RX core BUFFER FILL LEVEL
register for every JESD204C 64B66B lane in use.
Select the smallest value read from the BUFFER FILL LEVEL register and call this value BUF_FILL.
- If BUF_FILL falls between the Min and Max values (calculated at step 2), the
data arrival is within the safe TW and no further action is required. If however
the BUF_FILL does not fall between the Min and Max values, then the following
action should be taken.
- Program the SYSREF DELAY register with a delay value calculated as
follows:
If the BUF_FILL value is low, then the SYSREF DELAY value programmed should be increased by one or two as follows:
- If BUF_FILL = 0. Then SYSREF DELAY should be increased by two.
- If BUF_FILL = 1. Then SYSREF DELAY should be increased by one.
If the buffer is almost full, then the SYSREF DELAY value programmed should be increased by three or four (i.e., 1 or 2 plus the low margin of 2).
- Reset the JESD204C receive core and reinitialize the link. This step must be performed before the modified SYSREF_DELAY value will affect the LEMC.
- Re-read the BUFFER FILL LEVEL register for every lane to confirm the
data arrival is now within the target window.
When configuring this link, the calculated SYSREF DELAY value should be stored for future use.
- Program the SYSREF DELAY register with a delay value calculated as
follows: