The maximum number of lanes per link is eight. For interfaces which require more than eight lanes, simply create multiple cores with a maximum of eight lanes each.
For 8B10B transmit interfaces, the lane ID and number of lanes per link ILAS parameters for each lane can be independently programmed using the Lane ID registers.
For 8B10B receive interfaces, the lane ID and number of lanes per link parameters for each lane can be read from the LID and L fields of the RX_ILA_CFG3 register for each lane.
This programmable Lane ID and number of lanes per link feature for 8B10B cores can also be used to share a single JESD204C core with multiple synchronous converters. For example, eight one lane converters might be connected to a single JESD204C core. If this is an 8B10B transmitter core, the Lane IDs can all be programmed to be lane 0 with 1 lane per link (value = 0). For 64B66B cores, there are no Lane IDs so this is not applicable.