JESD204_PHY Outclocks for UltraScale+/UltraScale Devices - 4.2 English

JESD204C LogiCORE IP Product Guide (PG242)

Document ID
PG242
Release Date
2023-11-06
Version
4.2 English

The JESD204_PHY IP core generates the clocks and rxoutclk at the correct frequency to use as core_clk. However, the output phase of these clocks varies from reset to reset. This means that for JESD204 interfaces, the JESD204_PHY IP core outclock ports might only be used to drive core_clk when Subclass 0 is used, and deterministic latency is not required. For systems that require deterministic latency and therefore use Subclass 1 or Subclass 2, the JESD204_PHY IP core outclocks should not be used.