JESD204 PHY Configuration Tab for UltraScale+/UltraScale Devices - 4.3 English - PG242

JESD204C v4.3 LogiCORE IP Product Guide (PG242)

Document ID
PG242
Release Date
2025-12-03
Version
4.3 English
Figure 1. JESD204 PHY Tab
Transceiver Parameters
For any selected Line Rate and PLL Type, valid Reference Clock frequencies can be selected from a drop-down list. A free-running DRP clock must be supplied, and the frequency (within the displayed valid range) must be entered in the DRP Clock Frequency box.