Core Specifics |
Supported Device Family
1
|
Versal adaptive SoCs,
UltraScale+,
UltraScale
|
Supported User Interfaces |
AXI4-Lite, AXI4-Stream
|
Resources |
Performance and Resource Utilization web
page
|
Provided with
Core
|
Design Files |
Encrypted RTL |
Example Design |
Verilog |
Test Bench |
Verilog |
Constraints File |
XDC |
Simulation Model |
Verilog |
Supported S/W Driver |
N/A |
Tested Design
Flows
2
|
Design Entry |
AMD Vivado™ Design Suite
|
Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
Synthesis |
Vivado Synthesis |
Support |
Release Notes and Known Issues |
Master Answer Record: 68804
|
All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
Xilinx
Support web page
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|