- For AMD Versal™
Adaptive SoCs, ensure
that the core is correctly wired up and that Block Automation has been used to connect up
the Versal Adaptive SoC Transceiver when using the
Legacy GT Wizard.
- For AMD UltraScale+™
and AMD UltraScale™
devices, ensure that the core is correctly wired up and that the lane based signals are
wired to the correct location on the JESD204_PHY.
- Ensure that all the timing constraints for the core were met during
implementation.
- Ensure that all clock sources are clean and in particular that the
transceiver reference clocks meet the transceiver requirements from the appropriate FPGA
Data Sheet.
- Ensure all clock sources are stable before deasserting the external
reset signal to the core.
- For UltraScale+ and UltraScale devices,
ensure that all transceiver PLLs have obtained lock by monitoring the
QPLLLOCK_OUT and/or CPLLLOCK_OUT port either using the debug feature or by routing the signals to
a spare pin.