Features - Features - 4.3 English - PG242

JESD204C v4.3 LogiCORE IP Product Guide (PG242)
Document ID
PG242
Release Date
2025-12-03
Version
4.3 English
  • Designed to JEDEC® JESD204C.1 Standard
  • Supports GTY, GTYP, and GTM (NRZ only) transceivers on AMD Versal™ adaptive SoCs
  • Supports GTH and GTY transceivers on AMD UltraScale+™ and AMD UltraScale™ devices
  • Supports up to eight lanes per core and greater number of lanes using multiple cores
  • Supports 64B66B and 8B10B link layers
  • Supports FEC Encoding (TX) and Decoding (RX) on the 64B66B link layer
  • Supports CRC-12, CMD and FEC meta data modes on the 64B66B link layer
  • Supports subclass 0 and 1 on the 64B66B link layer and Subclass 0,1, and 2 on the 8B10B link layer
  • Provides physical and data link layer functions when used with the Versal Adaptive SoC Transceiver Wizard or GT Wizard subsystem and the JESD204_PHY core for UltraScale and UltraScale+ devices
    Note: The Versal Adaptive SoC Transceiver Wizard/GT Wizard subsystem is used directly by the JESD204C core and the JESD204_PHY is no longer required.
  • AXI4-Lite configuration interface
  • AXI4-Stream Data and Command interfaces
  • Supports Transceiver sharing between TX and RX cores using the JESD204_PHY core or Versal Adaptive SoC Transceiver Wizard/GT Wizard subsystem