Example Design - 4.2 English

The JESD204C IP can be generated as a TX or RX configuration with either 64B66B or 8B10B linecoding. All selections include a lightweight test harness to enable familiarization with the design and signal interface.

To create the example design for AMD Versal™ adaptive SoCs:

1. In AMD Vivado™ , create a new block design in IP integrator.
2. Add the JESD204C IP core to the canvas.
3. Select the JESD204C IP core and configure exactly as required.
4. Right-click the JESD204C IP, and select Open IP Example Design, from the drop-down menu as shown in the following figure. This opens a new Vivado project containing the complete RX or TX design example.

Figure 1. Opening the Example Design

To create the example design for AMD UltraScale+™ and AMD UltraScale™ devices:

1. In Vivado, create a new empty project.
2. Select the FPGA part that you wish to use.
3. Using the Vivado IP catalog, select the JESD204C IP core and configure exactly as required.
4. Right-click the block under Design Sources, and select Open IP Example Design, from the drop-down menu as shown in the following figure. This opens a new Vivado project containing the complete RX or TX design example.

Figure 2. Opening the Example Design

The following figures show an overview of the example design created for both a JESD204C TX and an JESD204C RX core. The design contains a full transmit and receive path example sharing a Versal Adaptive SoC Transceiver or JESD204_PHY core. The design will generate the JESD204C TX or RX core as configured in the IP catalog. A matching JESD204C TX or RX core will also be generated with settings to complement.

The design is composed of the following main blocks:

• An AXI4-Lite interconnect block to provide multiplexed access to the TX, RX and PHY AXI4-Lite interfaces.
• A simple pattern generator that generates analog sample data and control bits.
• An example mapper that demonstrates mapping the analog sample data and control words into the JESD204C transport layer on the AXI4-Stream interface to drive the TX core.
• (Only in 64B66B cores.) A simple command word generator that passes commands to the TX core. These commands are aligned with the values from the data generator.
• A JESD204C TX core (configuration set in the JESD204C core IP catalog).
• A Versal Adaptive SoC Transceiver core (configuration set in the JESD204C core GUI GT Wizard Configuration tab) (Figure 3).
• A JESD204_PHY core (configuration set in the JESD204C core GUI PHY Configuration tab) (Figure 4).
• A JESD204C RX core (configuration set in the JESD204C core IP catalog).
• An example demapper that demonstrates the AXI4-Stream interface and the JESD204C transport layer back to analog samples and control words.
• A simple pattern checker that checks the received sample and control words for correctness.
• (Only in 64B66B cores.) A simple command word checker that checks the received command word for correctness.

Figure 3. Core Example Design for Versal Adaptive SoCs

Figure 4. Core Example Design for UltraScale+/UltraScale Devices