The following figure shows the result of running Block Automation on two JESD204C cores, one TX and one RX. The JESD204C cores are running at different line rates and therefore have been configured so that one uses the RPLL and the other the LCPLL.
Note: To see the case where both TX and RX cores
sharing a Transceiver are running at the same line rate, generate the IP example design
(see Example Design) in the Vivado IDE.
Figure 1. Block Automation on a TX JESD204C Core and RX JESD204C Core
Running at Different Line Rates
