Data and Command Interfaces - 4.3 English - PG242

The transmitter and receiver cores incorporate AXI4-Stream interfaces for data ingress and egress. These AXI4-Stream interfaces include data and flow control signals only. In addition, there are supplementary control signals that are used to signal the timing of the data on the AXI4-Stream interface.

The AXI data input and output by the core contains 4-bytes per clock cycle per lane for 8B10B and 8-bytes per clock cycle per lane for 64B66B. The least significant byte position in each 32-bit or 64-bit block holds the first byte received from the ADC or transmitted to the DAC. The following figure shows an example of how AXI4-Stream data is mapped on to JESD204C using 8B10B encoding.

Figure 1. 8B10B Encoding - 4 Lane DAC, Frame size (F) = 1, 16 Bit I and Q with I Sample in Lanes 0 & 1 and Q Sample in Lanes 3 & 4

The following figure shows an example of how AXI4-Stream data is mapped on to JESD204C using 64B66B encoding.

Figure 2. 64B66B Encoding - 4 Lane DAC, Frame size (F) = 1, 16 Bit I and Q with I Sample in Lanes 0 & 1 and Q Sample in Lanes 3 & 4

For a 64B66B transmitter, the following figure shows the timing of the tx_soemb (Start Of Extended Multiblock) signal relative to the AXI4-Stream data tx_tdata and tx_cmd_tdata. The tx_soemb signal is a single bit and it is set High in the cycle preceding the first data block of an extended multiblock. The data interface will transfer one 64-bit block B every core clock cycle. The command interface will transfer one command word (either 19-bit or 7-bit) every multiblock. If data is not available on the command interface (tx_cmd_tvalid = 1), then an IDLE command will be transmitted. The command interface has been padded out to 32 bits per lane. Only bits [18:0] or [6:0] are actually used, and all unused bits are set to 0.

Figure 3. 64B66B Transmit Data Interface Timing

For a 64B66B receiver, the following figure shows the timing of the rx_soemb signal relative to the AXI4-Stream data rx_tdata. The rx_soemb signal is a single bit, and it is set High in the cycle preceding the first data block of an extended multiblock. The command interface will transfer one word every multiblock.

Figure 4. 64B66B Receive Data Interface Timing

For a 8B10B transmitter, the following figure shows the timing of tx_sof (Start Of Frame) and tx_somf (Start Of Multiframe) signals relative to the AXI data tx_tdata. tx_sof and tx_somf are fixed at four bits wide because the internal data width of each lane is 32 bits, and the start of frame (or multiframe) can occur in any of the four byte positions of the 32-bit word. For multilane configurations, the start of frame (or multiframe) signal indicates the byte position of the first byte of a frame in tx_tdata[31:0], tx_tdata[63:32], tx_tdata[95:64], etc. For example, in a four lane configuration when tx_sof = 0001, the first byte of four new frames appears in tx_tdata in a single cycle, tx_tdata[7:0], tx_tdata[39:32], tx_tdata[71:64], and tx_tdata[103:96].

Figure 5. 8B10B Transmit Data Interface Timing for F = 8 and K = 4

For a 8B10B receiver, the following figure shows the timing of rx_sof (Start Of Frame) and rx_somf (Start Of Multiframe) signals relative to the AXI data rx_tdata. rx_sof and rx_somf are fixed at four bits wide because the internal data width of each lane is 32 bits, and the start of frame (or multiframe) can occur in any of the four byte positions of the 32-bit word. For multilane configurations, the start of frame (or multiframe) signal indicates the byte position of the first byte of a frame in rx_tdata[31:0], rx_tdata[63:32], rx_tdata[95:64], etc. For example, in a four lane configuration when rx_sof = 0001, the first byte of four new frames appears in rx_tdata in a single cycle, rx_tdata[7:0], rx_tdata[39:32], rx_tdata[71:64], and rx_tdata[103:96].

Figure 6. 8B10B Receive Data Interface Timing for F = 8 and K = 4