DRP Clock for UltraScale+/UltraScale Devices - DRP Clock for UltraScale+/UltraScale Devices - 4.3 English - PG242

JESD204C system implementation requires the use of a JESD204 PHY core. The JESD204_PHY core must be supplied with a DRP clock (see JESD204 PHY LogiCORE IP Product Guide (PG198)).