DAC Timing - 4.2 English

JESD204C LogiCORE IP Product Guide (PG242)

Document ID
PG242
Release Date
2023-11-06
Version
4.2 English

The key parameters of the DAC receiver required to calculate end to end latency are:

  1. The fixed delay from SYSREF to LEMC (TRXLEMC)
  2. The delay from JESD204C input to LEMC (TRXIN)
  3. The fixed delay from LEMC to analog output (TRXOUT)

    The delay from SYSREF to LEMC and from LEMC to output must be fixed for a Subclass 1 device, but the delay from JESD204C serial data into LEMC can vary because the receiver buffer compensates for variations in end to end latency. See the following figure.

Figure 1. DAC RX Timing