Customizing and Generating the Core - 4.2 English

This section includes information about using AMD tools to customize and generate the core in the AMD Vivado™ Design Suite.

For AMD Versal™ adaptive SoCs, the core should be used in IP integrator, because this is the only supported flow to allow IP integrator Block Automation to generate and correctly configure Versal adaptive SoC Transceiver cores as required. This is also required to enable transceiver sharing with other JESD cores (TX and RX) and other IP cores.

For AMD UltraScale+™ /AMD UltraScale™ devices, if you are customizing and generating the core in the IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information.

IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, you can run the validate_bd_design command in the Tcl Console.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

1. Select the IP from the IP catalog.
2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.