Core Timing - 4.2 English

The key parameters of the FPGA transmitter required to calculate end to end latency are:

1. The fixed delay from SYSREF to LEMC (T_TXLEMC)
2. The fixed delay from AXI input to LEMC (T_TXIN)
3. The delay from LEMC to JESD204C serial output (T_TXOUT)

   The delay from SYSREF to LEMC and AXI data into LEMC must be fixed for a Subclass 1 device, but the delay from LEMC to JESD204C serial data out can vary because it is compensated for in the receiver during alignment to LEMC. See the following figure.