Core Timing - 4.2 English

JESD204C LogiCORE IP Product Guide (PG242)

Document ID
PG242
Release Date
2023-11-06
Version
4.2 English

The key parameters of the FPGA transmitter required to calculate end to end latency are:

  1. The fixed delay from SYSREF to LEMC (TTXLEMC)
  2. The fixed delay from AXI input to LEMC (TTXIN)
  3. The delay from LEMC to JESD204C serial output (TTXOUT)

    The delay from SYSREF to LEMC and AXI data into LEMC must be fixed for a Subclass 1 device, but the delay from LEMC to JESD204C serial data out can vary because it is compensated for in the receiver during alignment to LEMC. See the following figure.

Figure 1. FPGA TX Timing