The AMD LogiCORE™ IP JESD204C core implements a JESD204C link layer. When used with the LogiCORE IP Versal Adaptive SoC Transceiver Wizard or JESD204_PHY core (to provide the physical layer), a JESD204C system can be created supporting line rates between 1 and 32.5 Gbps on one to eight lanes using Versal adaptive SoC GTY, GTYP, and GTM transceivers or AMD UltraScale+™ and AMD UltraScale™ transceivers (both GTH and GTY).
See the device data sheets for maximum line rates supported by each device and family. The JESD204C core can be configured as transmit or receive, using either 64B66B or 8B10B linecoding, and multiple cores can be used to realize links requiring more than eight lanes.
The JESD204C core is delivered by using the AMD Vivado™ Design Suite. In addition, an example design is provided in Verilog.