This section describes how to constrain a design containing the JESD204C core. This is accomplished by using the XDC delivered with the core at generation time. An additional XDC file is generated with the IP example design; only the core XDC file should be used in user designs.
Required Constraints
This section defines the constraint requirements for the core. Constraints are provided in several XDC files which are delivered with the core and the example design to give a starting point for constraints for the user design.
There are four XDC constraint files associated with this core:
- <corename>_example_design.xdc
- <corename>_ooc.xdc
- <corename>.xdc
- <corename>_clocks.xdc
The first file is used only by the example design; the second file is used for Out-Of-Context support where this core can be synthesized without any wrappers; the third file is the main XDC file for this core. The last file defines constraints which depend on clock period definition, either those defined by other XDC files or those generated automatically by the AMD tools, and this XDC file is marked for automatic late processing within the Vivado design tools to ensure that definitions exist.
Device, Package, and Speed Grade Selections
See the appropriate device data sheet listed in References to determine the maximum line rate supported. Not all devices, packages, and speed grades can operate at the maximum line rate supported by the IP.
Clock Frequencies
The reference clock and core clock frequency constraints vary depending on the selected line rate and reference clock when generating the core. See the generated XDC for details.
Clock Domains
There are also several paths where clock domains are crossed. These include the management interface. See the generated XDC file for details.
Clock Management
Reference clock and core clock resources require location constraints appropriate to your top-level design.
Clock Placement
Reference clock input should be given location constraints appropriate to your top-level design and to the placement of the transceivers.
Core clock input (if required) should be given location constraints appropriate to your top-level design.
Banking
All ports should be given location constraints appropriate to your top-level design within banking limits.
Transceiver Placement
Transceivers should be given location constraints appropriate to your design.
I/O Standard and Placement
All ports should be given I/O standard and location constraints appropriate to your top-level design.