Configuring the JESD204 PHY in IP Integrator for UltraScale+/UltraScale Devices - 4.3 English - PG242

JESD204C v4.3 LogiCORE IP Product Guide (PG242)

Document ID
PG242
Release Date
2025-12-03
Version
4.3 English

The example design that can be generated for the JESD204C core in Vivado (see Example Design) delivers a JESD204 PHY core with the settings used from the JESD204C GUI. When configuring a JESD204 PHY core for use with a JESD204C core, the subsequent values must be set as shows in the following image:

  • The transceiver type must be set to GTHE3, GTHE4, GTYE3, or GTYE4.
  • The JESD204 Version is hard-coded to JESD204C as the JESD204 IP is discontinued.
  • The line coding must be set to 64B66B or 8B10B.
  • The line rate must be set to the same value as defined in the JESD204C GUI.
Figure 1. JESD204 PHY GUI

It is possible to share a JESD204 PHY between different instances of JESD204C cores. The TX and RX are configured separately and can therefore run at different line rates and line coding standards.