Figure 1. Configuration Tab for Versal Adaptive
SoCs
Figure 2. Configuration Tab for UltraScale+/UltraScale Devices
- Component Name
- The component name is used as the base name of the output files generated for the core. Names must begin with a letter and must be composed from these characters: a through z, 0 through 9, and “_” (underscore).
- Transmit or Receive
- The core can be configured as a transmitter, for connection to DAC devices, or receiver, for connection to ADC devices.
- Lanes per Link (L)
- The core supports one to eight lanes. For interfaces requiring more than eight lanes, multiple cores must be used.
- Line Coding
- The core supports 64B66B and 8B10B linecoding modes.
- Include FEC
- (64B66B only.) Check this option to include the FEC Encoder (TX) or Decoder (RX) in the core. Including the FEC core will increase the resources required by the core.
- AXI4-Lite Clock Frequency
- The frequency of the clock connected to the AXI4-Lite Management Interface.
- Include RPAT
- (8B10B Transmitter only.) Check this option to include the logic required to generate a Modified Random test pattern. This option will increase the resources required by the core.
- Include JSPAT
- (8B10B Transmitter only.) Check this option to include the logic required to generate a Scrambled Jitter test pattern. This option will increase the resources required by the core.