Combining Multiple JESD204C Cores - 4.3 English - PG242

Implement the following design features to combine multiple JESD204C cores.

1. Register the SYSREF input and drive the IP cores from the registered signal. One register can be used in the IO to capture the external signal and a second one in the fabric that can be replicated by the fitter if necessary to help meet timing.
2. For 64B66B TX JESD204C cores, AND the tx_tready outputs from all cores to produce a single tx_tready signal. Use the ANDed tx_tready to gate the input tx_tdata to all JESD204C TX cores.
3. For 64B66B RX JESD204C cores, AND the rx_tvalid outputs from all cores to produce a single rx_tvalid. Use the ANDed rx_tvalid to gate the output rx_tdata from all JESD204C RX cores.

The following example shows two 64B66B TX JESD204C cores combined in this way.

You must start the system in the following order:

1. Do a complete reset of cores. Pole the reset registers to confirm.
2. Enable SYSREF. The cores capture SYSREF on the rising edge of the core clock.
3. Ensure cores achieve Sync Header Lock and Extended Multiblock Lock.
4. Follow the procedure described in section Achieving Repeatable Latency to ensure there is no latency variation between the cores.
5. Enable the JESD204C Data and Command interfaces independently using the AXI interface.

Following the above procedure ensure that even if the Data and Command interfaces of the two cores (as shown in the previous figure) are enabled at different times, because the ingress and egress timing of the cores is synchronized using SYSREF, the latency through the cores is the same.

By ANDing all the tx_tready signals (TX cores) and the rx_tvalid signals (RX cores), it is possible to ensure that data is never propagated through one core without the other, and that partially valid data is never fed through the system.

In the previous figure, the TX0 data interface is enabled before TX1 data interface. The Extended Multi-Blocks (EMBs) A, B, and C are aligned between the cores using SYSREF but the individual data paths started at different times. This results in EMB A not being transferred through TX1. When the ANDed version of the tx_tready outputs is used instead of the individual ones, the cores propagates the EMBs together. Timing does not change, but both TXs have to assert the tx_tready signal before any data transfer through cores can take place. This helps ensure that partially valid data is never fed through the system.

The previous figure shows the RX use case. The principle is the same as for TX but you must AND the rx_tvalid output signals instead. In the above figure RX1 is enabled after RX0 resulting in rx_tvalid[1] asserting HIGH after the transfer of EMB A. You can ignore the partially valid data from RX0 using the ANDed rx_tvalid signal until both cores have valid data.

8B10B Cores

Following are some key differences for 8B10B cores:

• Cores achieve 8B10B SYNC and Code Group Sync, instead of SH Lock and EMB Lock.
• 8B10B JESD204C Data interface is enabled automatically, there is no manual control.
• There is no need to AND the tx_tready or rx_tvalid signals. You must only ensure that each 8B10B core is aligned and the signals tx_tready and rx_tvalid assert HIGH on the same core_clock cycle provided you follow the procedure described in section Achieving Repeatable Latency.