- Always refer to the device data sheet for the chosen part and speed
grade to confirm which PLLs are available for a required line rate; PLL selection
for a particular rate might not be arbitrary.
Versal adaptive SoCs:
- If the RPLL is required, the transceiver reference clock cannot be used as the core clock when the core is configured for 64B66B linecoding because the acceptable reference clock input frequencies to the RPLL do not cover the required Line Rate/66 ratio. This restriction does not apply when the core is configured for 8B10B linecoding.
UltraScale+/UltraScale:
- If the CPLL is required, the transceiver reference clock cannot be used as the core clock when the core is configured for 64B66B linecoding because the acceptable reference clock input frequencies to the CPLL do not cover the required Line Rate/66 ratio. This restriction does not apply when the core is configured for 8B10B linecoding.
- For Line rates above 16.375 Gbps, ensure only port
MGTREFCLK0is used to drive QPLL0, andMGTREFCLK1to drive QPLL1.