The synchronous capture of SYSREF is critical to the deterministic latency mechanism of
JESD204C. By default, no constraints are applied to the SYSREF input. However, the
required timing of the SYSREF input can be checked using the
report_datasheet
command in the Vivado Design Suite.
An example timing diagram is shown in the following figure. This example uses the following settings:
core_clk
period = 6.4 ns (6.25 Gb/s line rate with 8B10B
linecoding)
In this example, the report_datasheet
command gives a setup of 4.6 ns
and hold of -1.5 ns for the SYSREF pin.
The easiest method to ensure a design will be able to reliably capture SYSREF is to use a programmable clock generator chip that allows fine delay adjustment of its outputs, to generate all the JESD204C clocks and SYSREF signals in the system. This will allow for the delay between core clock and SYSREF to be adjusted to meet the setup and hold requirements achieved by your design.
It is also possible to use an MMCM to adjust the phase of core clock internally to align with the setup and hold requirements.