The following examples show what results from running Block Automation.
Versal Adaptive SoC Transceiver GT Quad will be created with the correct settings required for the selected JESD204C IP cores.
- JESD204C IP cores will be connected to the Versal Adaptive SoC Transceiver GT Quad.
- The Versal Adaptive SoC
Transceiver Register Configuration Interface is automatically configured as AXI in
Block Automation. To change this to an APB3 interface, run the following Tcl command
in the Tcl Console.
set_property -dict [list CONFIG.REG_CONF_INTF {APB3_INTF} ] [get_bd_cells gt_quad_base_0]
The remaining unconnected ports such as ref_clock, core_clk, resets and sysref, etc. then need to be connected up manually. For an
example of how to connect up the remaining ports, generate the IP example design (see
Example Design) in Vivado and use this as a reference.