AXI4-Lite Interface Clock - 4.2 English

JESD204C LogiCORE IP Product Guide (PG242)

Document ID
PG242
Release Date
2023-11-06
Version
4.2 English

The JESD204C core is configured and monitored through an AXI4-Lite processor interface. The clock for this interface is separate and independent from the core and reference clocks. The AXI4-Lite clock must be a free running clock as it is also used to clock the reset circuitry. The valid range is between 10 MHz and 200 MHz.