While upgrading from AMD UltraScale™ /AMD UltraScale+™ PCIe PHY IP to Versal adaptive SoC PCIe PHY IP, consider the following ports for mapping and integrating with the PCIe MAC:
MAC/PIPE Interface | ||||
---|---|---|---|---|
Name | Direction | Width | UltraScale/UltraScale+ | Versal |
PHY_REFCLK | I | 1 | YES | YES |
PHY_GTREFCLK | I | 1 | YES | YES |
PHY_PCLK | O | 1 | YES | YES |
PHY_CORECLK | O | 1 | YES | YES |
PHY_USERCLK | O | 1 | YES | YES |
PHY_MCAPCLK | O | 1 | YES | YES |
PIPE_USERCLK2 | O | 1 | NO | YES |
PHY_RST_N | I | 1 | YES | YES |
PHY_TXP | O | 1-bit per lane | YES | YES |
PHY_TXN | O | 1-bit per lane | YES | YES |
PHY_RXP | I | 1-bit per lane | YES | YES |
PHY_RXN | I | 1-bit per lane | YES | YES |
PHY_TXDATA | I | 64-bit per lane | YES | YES |
PHY_TXDATAK | I | 2-bit per lane | YES | YES |
PHY_TXDATA_VALID | I | 1-bit per lane | YES | YES |
PHY_TXSTART_BLOCK | I | 1-bit per lane | YES | YES |
PHY_TXSYNC_HEADER | I | 2-bit per lane | YES | YES |
PHY_RXDATA | O | 64-bit per lane | YES | YES |
PHY_RXDATAK | O | 2-bit per lane | YES | YES |
PHY_RXDATA_VALID | O | 1-bit per lane | YES | YES |
PHY_RXSTART_BLOCK | O | 1-bit per lane | YES | YES |
PHY_RXSYNC_HEADER | O | 2-bit per lane | YES | YES |
PHY_TXDETECTRX | I | 1-bit per lane | YES | NO |
PHY_TXDETECTRX_LOOPBACK | NO | YES. 3-bit per link for Versal. Same as PHY_DETECTRX | ||
PHY_TXELECIDLE | I | 1-bit per lane | YES | YES |
PHY_TXCOMPLIANCE | I | 1-bit per lane | YES | YES |
PHY_RXPOLARITY | I | 1-bit per lane | YES | YES |
PHY_POWERDOWN | I | 2-bit per lane | YES | YES |
PHY_RATE | I | 2/3-bit per lane | YES. 2-bit per link for UltraScale/UltraScale+ | YES. 3-bit per link for Versal |
PHY_RXTERMINATION | I | 1-bit per lane | NO. In UltraScale/UltraScale+ it is not exposed outside. Driven inside PCIe PHY wrappers | YES. It is from PCIe MAC. RX Termination Control. To be driven 1b during RX Detect. 0b in all other states |
PHY_RXVALID | O | 1-bit per lane | YES | YES |
PHY_PHYSTATUS | O | 1-bit per lane | YES | YES |
PHY_RXELECIDLE | O | 1-bit per lane | YES | YES |
PHY_RXSTATUS | O | 3-bit per lane | YES | YES |
PHY_READY | O | 1-bit per link | NO | YES. Indicates Master Lane PHY GT is ready |
PHY_TXMARGIN | I | 3-bit per lane | YES | YES |
PHY_TXSWING | I | 1-bit per lane | YES | YES |
PHY_TXDEEMPH | I | 1-bit per lane | YES | YES |
PHY_TXPRECURSOR | I | 5-bit per lane | YES. Always equalization wrappers in PCIe PHY wrappers | YES. It is from XILINX PCIe MAC that is, when phy_use_xilinx_mac is TRUE |
PHY_TXMAINCURSOR | I | 7-bit per lane | ||
PHY_TXPOSTCURSOR | I | 5-bit per lane | ||
PHY_TXEQ_CTRL | I | 2-bit per lane | YES. Always equalization wrappers in PCIe PHY wrappers | YES. Use only when using third-party PCIe MAC. As TX Equalization modules are inside the PCIe PHY IP that is, when phy_use_xilinx_mac is FALSE |
PHY_TXEQ_PRESET | I | 4-bit per lane | ||
PHY_TXEQ_COEFF | I | 6-bit per lane | ||
PHY_TXEQ_FS | O | 6-bit | ||
PHY_TXEQ_LF | O | 6-bit | ||
PHY_TXEQ_NEWCOEFF | O | 18-bit per lane | ||
PHY_TXEQ_DONE | O | 1-bit per lane | ||
PHY_RXEQ_CTRL | I | 2-bit per lane | YES. Always equalization wrappers in PCIe PHY wrappers | YES. Use only when using third-party PCIe MAC. As TX equalization modules are inside the PCIe PHY IP that is, when phy_use_xilinx_mac is FALSE |
PHY_RXEQ_TXPRESET | I | 4-bit per lane | ||
PHY_RXEQ_PRESET_SEL | O | 1-bit per lane | ||
PHY_RX_NEW_TXCOEFF | O | 18-bit per lane | ||
PHY_RXEQ_DONE | O | 1-bit per lane | ||
PHY_RXEQ_ADAPT_DONE | O | 1-bit per lane | ||
PHY_RXEQ_LFFS | I | 6-bit per lane | NO | |
PHY_RXEQ_LFFS_SEL | O | 1-bit per lane | NO | |
PHY_RXEQ_PRESET | I | 3-bit per lane | NO | |
PHY_RX_MARGIN_REQ_CMD | I | 4-bit per quad | NO | YES. RX Margin signals. New in Versal |
PHY_RX_MARGIN_REQ_LANE_NUM | I | 2-bit per quad | NO | |
PHY_RX_MARGIN_REQ_PAYLOAD | I | 8-bit per quad | NO | |
PHY_RX_MARGIN_REQ_REQ | I | 1-bit per quad | NO | |
PHY_RX_MARGIN_RES_ACK | I | 1-bit per quad | NO | |
PHY_RX_MARGIN_RES_CMD | O | 4-bit per quad | NO | |
PHY_RX_MARGIN_RES_LANE_NUM | O | 2-bit per quad | NO | |
PHY_RX_MARGIN_RES_PAYLOAD | O | 8-bit per quad | NO | |
PHY_RX_MARGIN_RES_REQ | O | 1-bit per quad | NO | |
PHY_RX_MARGIN_REQ_ACK | O | 1-bit per quad | NO | |
PCIE_LTSSM_STATE | I | 6-bit per link | NO | YES |
PCIE_LINK_REACH_TARGET | I | 1-bit per link | NO | YES |
gt_gtpowergood | O | 1-bit per lane | YES | No. If required, this can be taken from GTY/P QUAD |
as_mac_in_detect | I | 1-bit | YES | NO |
as_cdr_hold_req | I | 1-bit | YES | NO |