Resets - Resets - 1.0 English - PG239

To successfully reset UltraScale GTH for PCIe® applications, the recommended PCIe reset scheme should be used.

• It is recommended that the MAC or upper layer reset the PHY after power-on and fatal error conditions.
• The reference clock must be stable during reset.
• Once system reset is detected and synchronized, the PHY must assert phystatus.

The following is an example of a x1 PCIe reset procedure:

1. Stay in IDLE state until system reset is released.
2. Assert [CPLL/QPLL] reset, [TX/RX] progdivreset and GT[TX/RX] reset until GT powergood is active-High.
3. Release [CPLL/QPLL] reset and wait for [CPLL/QPLL] lock to go active-High.
4. Release [TX/RX] progdivreset and wait for [TX/RX] progdivresetdone to go active-High.
5. Release GT[TX/RX] reset, assert [TX/RX] userrdy and wait for [TX/RX] resetdone to go active-High.
6. Start TX SYNC alignment. Extend txsync_start to four refclk cycles.
7. Wait for TXSYNC alignment to be done.
8. Wait for phystatus to get deasserted.
9. Connect the phystatus_rst output (communicates the completion of reset sequence) from the PHY to the PCIe MAC.
10. PCIe MAC reset is complete.