Revision History - Revision History - 3.0 English - PG238

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)
Document ID
PG238
Release Date
2025-11-20
Version
3.0 English

The following table shows the revision history for this document.

Section Revision Summary
11/20/2025 Version 3.0
Features New features support for Versal AI Gen2 devices
  • LPDT and ULPS Escape mode for DPHY and CPHY
  • CPHY mode – Upto 3 Lane support
  • CPHY command mode support
  • DPHY - LP support in BLLP blanking

New feature support for UltraScale+ and Versal

  • Command Long packet support upto 65532 bytes
  • YUV 422 16-bit and 20-bit data type support
Unsupported Features

Removed the following:

  • EoTp is not supported in command mode for AMD Versal Premium Series Gen 2 and Versal AI Edge Series Gen 2.
  • Mixing of short and long packets not supported in command mode for Versal AI Edge Series Gen 2 and Versal Premium Series Gen 2.

Updated the following:

LP mode in the BLLP region of Video transmission for CPHY is not supported.
User Parameters Added new parameters: DSI_CMD_FIFO
Register Space

Updated Protocol Configuration Register

  • Added YUV data types

Updated Interrupt Status Register

  • Removed sync fifo full
  • Renamed “async fifo full” to “byte fifo full”

Updated Status Register

  • Removed lpdt fifo full

Updated Command Queue Register

  • Bits [23:16] are used for command long packet word count [15:8]

Updated Interrupt Enable Register

  • Renamed async fifo full to byte fifo full
05/29/2025 Version 3.0
Features PHY mode – CPHY and Escape Mode added
IP Facts Added support for AMD Versal Premium Series Gen 2 and Versal AI Edge Series Gen 2.
Core Overview Updated Figure 1
Sub-core Details Added MIPI TX C-PHY/D-PHY
Unsupported Features Updated
Standards Added MIPI DSI spec v2.0
Ports Updated for Versal AI Edge Series Gen 2
Shared Logic Outside the Subsystem Added for Versal AI Edge Series Gen 2
User Parameters

Added new parameters:

C_PHY_MODE

C_EN_ESC_MODE

DPHY_ESC_CLK_PERIOD

DSI_BYTE_FIFO

Table 32: Interoperability Testing Added new boards VEK280 and SP701
12/04/2024 Version 3.0
Example Configuration 1 Updated Clock Frequency timing parameter and configuration calculations.
Example Configuration 2 Updated Clock Frequency timing parameter and configuration calculations.
Example Configuration 3 Updated Clock Frequency timing parameter and configuration calculations.
10/18/2023 Version 2.3
Ports Updated the section.
10/19/2022 Version 2.3
Timing Register-5 Added Register 0x6C to support higher VFP values.
04/26/2022 Version 2.2
D-PHY LP HS Offset Added Register 0x68 to consider D-PHY LP to HS Switching latency.
07/15/2021 Version 2.2
N/A Editorial update.
07/14/2021 Version 2.2
Features Updated section
Configuration Tab Updated section with a new parameter
User Parameters Updated Table 1with C_EN_CTS_TX parameter
02/04/2021 Version 2.2
N/A
  • Updated Configuration Tab screen for V2.2.
  • Added information for Line Rate (Mb/s).
  • Updated Default Line Rate (Mb/s) value for DHY_LINERATE to 800.
  • Added Versal (VCK190) information in Interoperability.
  • Updated Licensing and Ordering.
  • Updated Application Software Development.
07/14/2020 Version 2.1
IP Facts Added support for AMD Versal™ devices.
06/26/2020 Version 2.1
N/A
  • New clocking architecture for line rates above 1500 Mb/s, which removes need for ctrl_clk.
  • Relaxed restriction on input pixels per clock and data types for line rates above 1500 Mb/s.
10/30/2019 Version 2.0
N/A
  • Extended line rate support to 2500 Mb/s
  • Added DCS Long Packet Support
11/14/2018 Version 2.0
IP Facts Added Spartan 7 series support
Unsupported Features Added section
Shared Logic Outside the Subsystem Added an important note in the Shared Logic Outside the Subsystem section
Simulation Updated section
10/04/2017 Version 2.0
N/A
  • MIPI D-PHY serial pins grouped as interface
  • Board automation support added for FMC:LI-IMX274MIPI-FMC V1.0 which can be placed on ZCU102 FMC HPC0 slot. This FMC can interface MIPI AUO display.
04/05/2017 Version 1.1
N/A MIPI D-PHY 3.1 changes integrated
10/05/2016 Version 1.1
N/A
  • MIPI D-PHY 3.0 changes integrated
  • 7 series support
  • Details on Timing Register(s) calculation procedure and more than 4 Lane implementation added
04/06/2016 Version 1.0
Initial release. N/A