| Signal Name | Direction | Description |
|---|---|---|
| AMD Versal™ Premium Series Gen 2 and Versal AI Edge Series Gen 2 Shared Logic Outside Subsystem | ||
| mipi_phy_if/mipi_c_phy_if | O | TX-PHY Interface. |
| txwordclkhs_in | I | High-speed transmit word clock. |
| clkoutphy_in | I | PHY serial clock. |
| pll_lock_in | I | PLL lock indication. |
| txclkesc_in | I | Clock for escape mode operations. |
| clkoutphy_90_in | I | 90-degree phase shift of clkoutphy_in clock. |
| shared_pll_clkout0_in | I | High-speed mode clock for TX-PHY C-PHY Mode |
| Versal Premium Series Gen 2 and Versal AI Edge Series Gen 2 Shared Logic in the Subsystem | ||
| mipi_phy_if/mipi_c_phy_if | O | TX-PHY Interface. |
| txwordclkhs_out | O | High-speed transmit word clock. |
| clkoutphy_out | O | PHY serial clock. |
| pll_lock_out | O | PLL lock indication. |
| txclkesc_out | O | Clock for escape mode operations. |
| clkoutphy_90_out | O | 90-degree phase shift of clkoutphy_out clock. |
| mmcm_lock_out | O | MMCM lock indication. |
| UltraScale+ Shared Logic Outside Subsystem | ||
| mipi_phy_if | O | D-PHY interface. |
| txbyteclkhs_in | I | High-speed transmit byte clock. |
| clkoutphy_in | I | D-PHY serial clock. |
| pll_lock_in | I | PLL lock indication. |
| txclkesc_in | I | Clock for escape mode operations. |
| system_rst_in | I | An active-High system reset output to be used by the example design level logic. |
| UltraScale+ Shared Logic in the Subsystem | ||
| mipi_phy_if | O | D-PHY interface. |
| txbyteclkhs | O | High-speed transmit byte clock. |
| clkoutphy_out | O | D-PHY serial clock. |
| pll_lock_out | O | PLL lock indication. |
| txclkesc_out | O | Clock for escape mode operations. |
| system_rst_out | O | An active-High system reset output to be used by the example design level logic. |
| 7 series Shared Logic Outside Subsystem | ||
| mipi_phy_if | O | D-PHY interface. |
| txbyteclkhs_in | I | Input to D-PHY and used to transmit high-speed data. |
| oserdes_clk_in | I | Used to connect the CLK pin of TX clock lane OSERDES. |
| oserdes_clk90_in | I | Used to connect the CLK pin of TX data lane OSERDES and must have 90 phase shift with oserdes_clk_in. |
| oserdes_clkdiv_in | I | Used to connect the CLKDIV pin of TX clock lane OSERDES and must be generated from oserdes_clk_in as the source. |
| txclkesc_in | I | Clock used for escape mode operations. |
| system_rst_in | I | System level reset. |
| 7 series Shared Logic in Subsystem | ||
| mipi_phy_if | O | D-PHY interface. |
| txbyteclkhs | O | Clock used to transmit high speed data. |
| oserdes_clk_out | O | Used to connect the CLK pin of TX clock lane OSERDES. |
| oserdes_clk90_out | O | Used to connect the CLK pin of TX data lane OSERDES. It has 90 phase shift relationship with oserdes_clk_out. |
| oserdes_clkdiv_out | O | Used to connect the CLKDIV pin of TX clock lane OSERDES and generated from oserdes_clk_out as source. |
| mmcm_lock_out | O | MMCM lock indication. |
| txclkesc_out | O | Clock for escape mode operations. |
| Other Ports | ||
| system_rst_out | O | An active-High system reset output to be used by the example design level logic. |
| dphy_clk_200M | I | Fixed 200 MHz clock required for MIPI D-PHY. The same clock is used by s_axi interface of the subsystem. |
| s_axis_aclk | I | AXI4-Stream Video clock |
| s_axis_aresetn | I | AXI reset. Active-Low (Same reset for lite and stream interface). |
| s_axi_* | - | AXI4-Lite Interface |
| s_axis_tready | O | AXI4-Stream Interface |
| s_axis_tvalid | I | AXI4-Stream Interface |
| s_axis_tlast | I | AXI4-Stream Interface |
| s_axis_tdata | I |
AXI4-Stream Interface. Width of this port is dependent on pixel type and number of pixels per beat |
| s_axis_tkeep | I | Not used in the design. |
| s_axis_tuser | I |
AXI4-Stream Interface. TUSER[0] is used to map the Frame start signal of the AXI4-Stream Video Interface. The core does not use this signal, but generates Frame start packets based on timing registers programming. |
| System Interface | ||
| Interrupt | O | System Interrupt output. |