PHY LP HS Offset - PHY LP HS Offset - 3.0 English - PG238

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)
Document_ID
PG238
Release_Date
2026-07-13
Version
3.0 English

The core does not consider the LP to HS delay in the video timing calculations by default. Hence, you see slightly fewer frames per second (FPS) than intended. In situations where you need to consider the D-PHY LP to HS latency, you must program the following register.

The D-PHY LP to HS (more specifically the time from PPI signal txrequesths to txreadyhs) delay varies based on Line Rate (Mb/s), LPX Period (ns), internal design logic, and CDC stages.

User Inputs
  • P1 = UI in ns
  • P2 = LPX Period in ns
  • P3 = INT(PPI Byteclk in ns) is the calculation to convert the specified value into an integer number.
  • P4 = PPI Byteclk in ns (with decimal places)
Table 1. Internal Parameters L1
Line Rate L1
<150 INT(P1)
150 to <300 INT(P1*2)
301 to <600 INT(P1*4)
601 and above P3

L2 = P2 + 25

L3 = 85 + 6*P1

L4 = ((L3-3*L1)/5)-1 L5 = (L4*5 + L2)/P4

L6 = INT((105+6*P1)/P3) + 4

LP-HS delay = L5 + L6

The following table provides example LP‑HS delay values for certain line rates:

Table 2. Example LP-HS Delay for Certain Line Rates
Line Rate P1 P2 P3 L1 P4 L2 L3 L4 L5 L6 LP-HS Delay
80 12.5 50 100 12 100 75 160 23 1 5 6
150 6.666667 50 53 13 53.33333333 75 125 16 2 6 8
550 1.818182 50 14 7 14.54545455 75 95.90909091 13 9 12 21
1000 1 50 8 8 8 75 91 12 16 17 33
1188 0.841751 50 6 6 6.734006734 75 90.05050505 13 20 22 42
1440 0.694444 50 5 5 5.555555556 75 89.16666667 13 25 25 50

Due to CDC stages and decimal numbers of byte clk period, you might need to program a slightly higher or lower value obtained in the preceding table to get the closer FPS on the hardware.

LP-to-HS Delay for Versal AI Edge Series Gen 2 and Versal Premium Series Gen 2 Devices

Use the following user inputs to calculate the LP‑to‑HS delay for Versal AI Edge Series Gen 2 and Versal Premium Series Gen 2 devices. The calculations are same for both C-PHY and D-PHY.

User Inputs
  • P1 = 2 (CDC delay in word clocks)
  • P2 = LPX Period (ns)/word clock period
  • P3 = C_HS_ZERO (in word clocks)
  • P4 = C_PREPARE_TIME (in word clocks

LP-HS delay = P1 + P2 + P3 + P4

The following table provides example LP‑HS delay values for certain line rates:

Table 3. Example LP-HS Delay for Certain Line Rates for Versal AI Edge Series Gen 2 and Versal Premium Series Gen 2 Devices
Line Rate P1 P2 P3 P4 LP-HS Delay
400 2 2 2 2 8
800 2 5 4 4 15
1500 2 6 8 8 24
2500 2 10 13 13 38

The final value to program is “LP-HS Delay” * DSI Lanes.

Table 4. Video Timing (PHY LP HS offset) (0x68)
Bits Name Reset Value Access Description
31:16 Reserved N/A N/A Reserved
15:0 PHY LP HS offset 0x0 R/W Offsets the PHY LP to HS transition delay in the video timing calculations