MIPI DSI TX Controller Core Registers - MIPI DSI TX Controller Core Registers - 3.0 English - PG238

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)
Document ID
PG238
Release Date
2025-11-20
Version
3.0 English

The following table specifies the name, address, and description of each firmware addressable register within the MIPI DSI TX controller core.

Table 1. MIPI DSI TX Controller Core Registers
Address Offset Register name Description
0x00 Core Configuration Register Core configuration options
0x04 Protocol Configuration Register Protocol configuration options
0x08 Reserved  
0x0C Reserved  
0x10 Reserved  
0x14 Reserved  
0x18 Reserved  
0x1C Reserved  
0x20 Global Interrupt Enable Register Global interrupt enable registers
0x24 Interrupt Status Register Interrupt status register
0x28 Interrupt Enable Register Interrupt enable register
0x2C Status Register Status register
0x30 Command Queue Packet Packet Entry to command Queue.
0x34 Data FIFO Register Data FIFO register
0x38 Reserved  
0x3C Reserved  
0x40 Reserved  
0x44 Reserved  
0x48 Reserved  
0x4C Reserved  
0x50 Timing Register-1 Video timing 5
0x54 Timing Register-2 Video timing 5
0x58 Timing Register-3 Video timing 5
0x5C Timing Register-4 Video timing 5
0x60 Line Time Total Line time
0x64 BLLP Time Blanking packet payload size in bytes (WC) available during VSA,VBP,VFP lines
0x68 D-PHY LP HS Offset D-PHY LP HS offset register
0x6C Timing Register-5 Video timing 5
0x70 Reserved  
0x74 Reserved  
0x78 Reserved  
0x7C Reserved  
  1. Access type and reset value for all the reserved bits in the registers are read only with value 0.
  2. All register access should be word-aligned and no support for write strobe. WSTRB is not used internally.
  3. Only the lower 7-bits (for example, 6:0) of read and write address of AXI are decoded, which means accessing address 0x00 and 0x80 results in reading the same address of 0x00.
  4. Read and write access to an address outside of the above range does not return any error response.
  5. All video timing registers need to be appropriately programmed for the successful transfer of video data. For more details, refer to the provided driver API for programming details.