The Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) Transmitter Subsystem implements a DSI transmit interface in adherence to the MIPI DSI-2 Standard v2.0 (Type 4 architecture). The subsystem receives a pixel stream from an AXI4-Stream interface and inserts the required markers (such as hsync start, hsync end) in accordance with the DSI protocol and user-programmed options. The packet framed is sent over a MIPI D-PHY or C-PHY (compliant with the MIPI Alliance Standard for D-PHY/C-PHY Specification, version 2.0) transmitter based on the number of lanes you select. The subsystem allows fast selection of the top-level parameters and automates most of the lower level parameterization. The AXI4-Stream interface allows a seamless interface to other AXI4-Stream-based subsystems.