Interrupt Status Register - Interrupt Status Register - 3.0 English - PG238

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)
Document ID
PG238
Release Date
2025-11-20
Version
3.0 English

Captures different error/status information of the core.

Table 1. Interrupt Status Register (0x24)
Bits Name Reset Value Access Description
31:6 Reserved NA NA Reserved
5 ULPS State 0x0 R/W1C

0: Indicates that the lanes have exited the ULPS state or are not in the ULPS state

1: Indicates that the lanes are in the ULPS state
4 Reserved NA NA Reserved
3 Byte FIFO Full 0x0 R/W1C

Asserted when BYTE FIFO full condition detected as per the depth configured from GUI using the BYTE FIFO Depth Value.

Recommended depth configuration value is 2 * HACT value.

Note: Applicable for Versal AI Edge Series Gen 2 and Versal Premium Series Gen 2 devices only.
2 Command Queue FIFO Full 0x0 R/W1C 1 Asserted when command queue FIFO full condition detected.
1 Unsupported/Reserved Data type 0x0 R/W1C 1 Asserted when unsupported/reserved data types seen in command queue.
0 Pixel Data underrun 0x0 R/W1C 1 Byte stream FIFO starves for Pixel during HACT transmission. 2
  1. W1C – Write 1 to Clear (to clear register bit, you have to write 1 to corresponding bits).
  2. Pixel Data underrun is not expected during normal core operation, which implies that the rate of incoming data is insufficient to keep up with the outgoing data rate.