Implementing More Than 4-Lane DSI-TX Design - Implementing More Than 4-Lane DSI-TX Design - 3.0 English - PG238

The existing MIPI DSI TX Subsystem allows a maximum of four lanes. Guidelines to achieve DSI designs with higher lane requirements (for example, an eight-lane design) are listed below:

1. After the stream source, you need a splitter module that splits the incoming video stream into two streams; the left-half and the right-half image.
2. Each splitter output then feeds to one DSI 4 lanes instance.
3. The DSI 8-lane Receiver should follow the reverse to combine the images.
4. You need to program each DSI-TX 4 lanes instance timing parameters based on half image rather than full image timing parameters.
5. In DSI-RX, one DSI instance reconstructs the left half of the image and the other DSI instance reconstructs the right half of the image.
6. AMD does not support a synchronized mode for multiple MIPI DSI TX IPs.

   Each MIPI DSI TX IP operates independently, with its own FSM controlling data output timing, making synchronization between multiple instances unachievable.

7. For applications requiring synchronization, we recommend using the MIPI D-PHY TX IP along with a custom user-designed protocol IP.

   This approach allows users to manually control the data flow so that all MIPI D-PHY TX IPs receive data simultaneously.

8. For users who need to use two MIPI DSI TX IPs in their design:
   • Both MIPI DSI TX IPs must share the same PLL.
   • The s_axis_aclk and dphy_clk_200M should be generated from the same clock source and operate at the same frequency to maintain consistency.

The 8-lane implementation using two 4-lane MIPI DSI TX instances is shown in the following figure.