Case 6: Switching the core between Video/ULPS Mode - Case 6: Switching the core between Video/ULPS Mode - 3.0 English - PG238

core_en – bit 0 in Core Configuration Register (0x0)

ulps_mode – bit 6 in Core Configuration Register (0x0)

ulps_state – bit 5 in Interrupt Status Register (0x24)

If core_en = 0

• Enable ULPS and the core: set ulps_mode = 1 and core_en = 1.

If core_en = 1

• Enable ULPS: set ulps_mode = 1.

Once the lanes enter ULPS, the ulps_state ISR is asserted.

• Set ulps_mode = 0 and wait 1 ms for the ULPS exit.
• Clear the ulps_state ISR bit and read again to confirm that the exit occurred correctly.
  • If the ISR bit is cleared, it means the lanes have exited ULPS.
  • If not, the lanes are still in ULPS.

If core_en = 0

• Program the required timing registers.
• Set core_en = 1, ulps_mode = 0, and command_mode = 0.

If core_en = 1 and ulps_mode = 1

• Ensure the timing registers are programmed.
• Disable ULPS by following the above steps.