Case 5: Switching the core between Video/LPDT Mode - Case 5: Switching the core between Video/LPDT Mode - 3.0 English - PG238

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)
Document ID
PG238
Release Date
2025-11-20
Version
3.0 English

The following register bit configuration is required to enable this feature:

  1. command_mode – bit 3 in Core Configuration Register (0x0)
  2. core_en – bit 0 in Core Configuration Register (0x0)
  3. cmd_or_lpdt_mode_control – bit 14 in Protocol Configuration Register (0x4)
  4. LPDT Mode

    If core_en = 0

    • Enable command_mode and cmd_or_lpdt_mode_control bits.

    If core_en = 1 and command_mode = 0

    • Disable the core by setting core_en = 0.
    • Enable command_mode and cmd_or_lpdt_mode_control (i.e., set both to 1).
    • Re-enable the core by setting core_en = 1.
    Note: The procedure for writing short and long packets in LPDT mode is the same as in Case 4, involving short and long commands respectively.
  5. Video Mode

    If core_en = 0

    • Program the required timing registers.
    • Set core_en = 1 and command_mode = 0.

    If core_en = 1 and command_mode = 1

    • Wait for the command execution in progress (bit 11 of register 0x2C) to become 0.
    • Ensure timing registers are programmed.
    • Set command_mode = 0.