C-PHY Example Configuration for Sync Pulses - C-PHY Example Configuration for Sync Pulses - 3.0 English - PG238

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)

Document_ID
PG238
Release_Date
2026-07-13
Version
3.0 English

Consider an exemplary MIPI DSI Panel with the following specifications:

Table 1. MIPI DSI Panel Parameters
Parameter Value
MIPI Parameters
Line Rate 500 Ms/s (1142.857 Mb/s)
Data Type Compressed

1 byte or 8 bits

Video Mode Sync Pulses
Lanes 2
Timing Parameters
Horizontal Active 640 pixels
Horizontal Blanking 100 pixels
Vertical Active 480 lines
Vertical Blanking 15 lines
Frame Rate 60 fps
Clock Frequency 21.978 MHz
PPI Width 16

To generate the values and set timing registers, based on the preceding example configuration, do the following:

  1. Get HACT(WC) and VACT.
    HACT(WC) = Active pixels per line * Bits per pixel/8
             = 640*8/8 
             = 640 (decimal) -> 0x280 (HEX)
    VACT     = Active lines per frame
             = 480 (decimal) -> 0x1E0 (HEX)
  2. Get total line-time in pixel clock.
    Pixel Frequency         = 21.978 MHz
    Pixel clock period      = 1000/21.978 = 45.5 ns
    Total pixel in one line = 640+100     = 740 
    Total line time         = 740*45.5    = 33670 ns
  3. Calculate the blanking time.
    Line-rate in Mb/s          = Line-rate in Msps * 16/7 
                               = 500 * 16/7 = 1142.857 Mb/s
    
    Word clock (PPI) frequency = Line-rate (in Mb/s) / 16 
                               = 1142.857/16 = 71.428 MHz
    
    Word clock period in ns    = 1000/71.428 = 14 ns
    
    Number of Words            = Pixels * Bits per pixel / PPI_Width
                               = 640 * 8 / 16 = 320
    
    Active pixels per line (HACT) Duration (ns) = Number of words * Word clk Period / Lanes                       
                               = 320 * 14 / 2 = 2240 ns
    
    Blanking time              = Line-time - HACT Duration
                               = 33670 - 2240 = 31430 ns
    
    Number of Words to meet "Blanking time" of 31430 ns
                               = Blanking time * Lanes / (Word Period)
                               = 31430 * 2 / 14 = 4490
    
    Word Count (WC) in Bytes   = Number of Words * PPI_Width / 8
                               = 4490 * 16 / 8 = 8980
  4. Adjust the blanking WC based on Video mode.
    Video mode: Sync Pulses
    
    Consistent linetime for Blanking and Active regions is achieved by adjusting blanking word count. Active region has 1 short packet and 3 long packets whereas Blanking region has 1 short packet and 1 long packet. So, 1 Short Packet and 2 Long Packet header, CRC and SSS bytes are reduced from available word count.
    
    For Sync Pulses, One line is composed of HSS + HSA + HSE + HBP + HACT + HFP.
    
    Horizontal Sync Start (HSS) -> Short packet -> 2 * (Packet Header + Lanes * SSS) bytes
    = 2 * (6 + 2*2) = 20 bytes
    
    Each Long packet without payload-> 2 * (Packet Header + Lanes * SSS) + CRC + Lanes * SSS
    = 2 * (6 + 2*2) + 2 + 2*2 = 26 bytes
    
    Total bytes covered in header and footer = 2 * Short packets + 4 * Long packets
                                             = 2 * 20 + 4 * 26 = 144 bytes
    
    Available blanking WC                    = 8980 - 144 = 8836
  5. Divide the total available WC across available blanking parameters HSA, HBP, and HFP. Considering a ratio of 2:2:2 gives: (the values for HBP and HFP are the distribution of the horizontal blanking words across these parameters. In the examples, AMD tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays might have specific requirements. Consult the datasheet for your display).
    Horizontal Sync Active (HSA) = 2*8836/6 = 2945.3333 = 2945 (rounded)
    Horizontal Back Porch (HBP)  = 2*8836/6 = 2945.3333 = 2945 (rounded)
    Horizontal Front Porch (HFP) = 8836 - 2945 - 2945   = 2946
  6. Set the applicable horizontal timing registers with the preceding calculated values.
    HSA = 2945 (decimal) = 0xB81 
    HBP = 2945 (decimal) = 0xB81 
    HFP = 2946 (decimal) = 0xB82
  7. Divide the total available vertical blanking lines between VSA, VBP, and VFP.

    Considering a ratio of 1:1:1 gives: (the values for VSA, VBP, and VFP are the distribution of the vertical blanking lines across these parameters. In the examples, AMD tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays might have specific requirements. Consult the data sheet for your display).

    VSA = 5 (decimal) -> 0x05
    VBP = 5 (decimal) -> 0x05
    VFP = 5 (decimal) -> 0x05
  8. Consolidate a set of horizontal and vertical timing parameters for a DSI panel with 640x480@60 fps, 2-Lane, 500 Ms/s, Compressed data of 8-bit width, and Video clock of 21.978 MHz are as follows:
    HACT = 0x280
    HSA  = 0xB81
    HBP  = 0xB81
    HFP  = 0xB82
    
    VACT = 0x1E0
    VSA  = 0x05
    VBP  = 0x05
    VFP  = 0x05