Consider an exemplary MIPI DSI Panel with the following specifications:
| Parameter | Value |
|---|---|
| MIPI Parameters | |
| Line Rate | 1000 Ms/s (2285.71 Mb/s) |
| Data Type |
RGB888 3 bytes or 24 bits |
| Video Mode | Sync Events |
| Lanes | 3 |
| Timing Parameters | |
| Horizontal Active | 1920 pixels |
| Horizontal Blanking | 120 pixels |
| Vertical Active | 1200 lines |
| Vertical Blanking | 12 lines |
| Frame Rate | 60 fps |
| Clock Frequency | 148.349 MHz |
| PPI Width | 16 |
To generate the values and set timing registers, based on the preceding example configuration, do the following:
- Get HACT(WC) and
VACT.
HACT(WC) = Active pixels per line * Bits per pixel/8 = 1920*24/8 = 5760 (decimal) -> 0x1680 (HEX) VACT = Active lines per frame = 1200 (decimal) -> 0x04B0 (HEX) - Get total line-time in pixel
clock.
Pixel Frequency = 148.349 MHz Pixel clock period = 1000/148.349 = 6.741 ns Total pixel in one line = 1920+120 = 2040 (Active + Blanking Pixels) Total line time = 2040*6.741 = 13751.64 ns - Calculate the blanking
time.
Line-rate in Mb/s = Line-rate in Msps * 16/7 = 1000 * 16/7 = 2285.71 Mb/s Word clock (PPI) frequency = Line-rate (in Mb/s) / 16 = 2285.71/16 = 142.857 MHz Word clock period in ns = 1000/142.857 = 7 ns Number of Words = Pixels * Bits per pixel / PPI_Width = 1920 * 24 / 16 = 2880 Active pixels per line (HACT) Duration (ns) = Number of words * Word clk Period / Lanes = 2880 * 7 / 3 = 6720 ns Blanking time = Line-time - HACT Duration = 13751.64 - 6720 = 7031.64 ns Number of Words to meet "Blanking time" of 7031.64 ns = Blanking time * Lanes / (Word Period) = 7031.64 * 3 / 7 = 3013.56 Word Count (WC) in Bytes = Number of Words * PPI_Width / 8 = 3013.56 * 16 / 8 = 6027.12 = 6027 (rounded) - Adjust blanking WC based on Video
mode.
Video mode: Sync Events Consistent linetime for Blanking and Active regions is achieved by adjusting blanking word count. Active region has 1 short packet and 3 long packets whereas Blanking region has 1 short packet and 1 long packet. So, 1 Short Packet and 2 Long Packet header, CRC and SSS bytes are reduced from available word count. For Sync Events, VACT line is composed of HSS + HBP + HACT + HFP. Horizontal Sync Start (HSS) -> Short packet -> 2 * (Packet Header + Lanes * SSS) bytes = 2*(6 + 3*2) = 24 bytes Each Long packet without payload-> 2 * (Packet Header + Lanes * SSS) + CRC + Lanes * SSS = 2*(6 + 3*2 + 2) + 3*2 = 32 bytes Total bytes covered in header and footer = 1 * Short packets + 2 * Long packets = 1 * 24 + 2 * 32 = 88 bytes Available blanking WC = 6027 - 88 = 5939 - Divide the total available WC across available blanking
parameters HBP and HFP.
Considering a ratio of 5:1 gives: (the values for HBP and HFP are the distribution of horizontal blanking words across these parameters. In the examples, AMD tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays might have specific requirements. Consult the datasheet for your display).
Horizontal Back Porch (HBP) = 5939 * 5/6 = 4949.167 = 4949 (rounded) Horizontal Front Porch (HFP) = 5939 - 4949 = 990 - Set the applicable horizontal timing registers with the
preceding calculated
values.
HBP = 4949 (decimal) -> 0x1355 HFP = 990 (decimal) -> 0x3DE - Divide the total available vertical blanking lines between VSA,
VBP, and VFP.Considering a ratio of 1:1:1 gives: (the values for VSA, VBP, and VFP are the distribution of the vertical blanking lines across these parameters. In the examples, AMD tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays might have specific requirements. Consult the data sheet for your display).
VSA = 4 (decimal) -> 0x04 VBP = 4 (decimal) -> 0x04 VFP = 4 (decimal) -> 0x04 - Consolidate a set of horizontal and vertical timing parameters
for a DSI panel with 1920x1200 at 60 fps, 3-Lane, 1000 Ms/s, RGB888, and Video
clock of 148.35 MHz are shown as
follows:
HACT = 0x1680 HBP = 0x1355 HFP = 0x3DE VACT = 0x04B0 VSA = 0x04 VBP = 0x04 VFP = 0x04