C-PHY Example Configuration for Burst - C-PHY Example Configuration for Burst - 3.0 English

Consider an exemplary MIPI DSI Panel with the following specifications:

Table 1. MIPI DSI Panel Parameters
Parameter	Value
MIPI Parameters
Line Rate	500 Ms/s (1142.857 Mb/s)
Data Type	Compressed 1 byte or 8 bits
Video Mode	Burst Mode
Lanes	2
Timing Parameters
Horizontal Active	640 pixels Compressed pixels: 500 BLLP: 140 pixels
Horizontal Blanking	100 pixels
BLLP during Active region of Horizontal lines	140 pixels
Vertical Active	480 lines
Vertical Blanking	15 lines
Frame Rate	60 fps
Clock Frequency	21.978 MHz
PPI Width	16

Note: For compressed data type, you are expected to pump in the compressed data. The core passes through those stream of data without any conversion. In the current example, it is expected that the 640 pixels of input stream is compressed to 500 pixels.

To generate the values and set timing registers, based on the preceding example configuration, do the following:

Get HACT(WC) and VACT.

HACT(WC) = Active pixels per line * Bits per pixel/8
         = 500*8/8 
         = 500 (decimal) -> 0x1F4 (HEX)

BLLP(WC) = BLLP Pixels per line * Bits per pixel/8
         = 140*8/8
         = 140(decimal) -> 0x8C (HEX)

VACT     = Active lines per frame
         = 480 (decimal) -> 0x1E0 (HEX)

Get total line-time in pixel clock.

Pixel Frequency         = 21.978 MHz
Pixel clock period      = 1000/21.978 = 45.5 ns
Total pixel in one line = 500+140+100 = 740 
Total line time         = 740*45.5    = 33670 ns

Calculate the blanking time.

Line-rate in Mb/s          = Line-rate in Msps * 16/7 
                           = 500 * 16/7 = 1142.857 Mb/s
Word clock (PPI) frequency = Line-rate (in Mb/s) / 16 
                           = 1142.857/16 = 71.428 MHz
Word clock period in ns    = 1000/71.428 = 14 ns

Number of HACT Words       = Pixels * Bits per pixel / PPI_Width
                           = 500 * 8 / 16 = 250
Number of BLLP Words       = Pixels * Bits per pixel / PPI_Width
                           = 140 * 8 / 16 = 70

Active pixels per line (HACT) Duration (ns) = Number of HACT words * Word clk Period / Lanes                       
                           = 250 * 14 / 2 = 1750 ns
BLLP Duration              = Number of BLLP words * Word clk Period/ Lanes
                           = 70 * 14 / 2 = 490 ns

Blanking time(BLLP+Horizontal Blanking) = Line-time - HACT Duration - BLLP Duration
                           = 33670 - 1750 - 490 = 31430 ns

Number of Words to meet "Blanking time" of 31430 ns
                           = Blanking time * Lanes / (Word Period)
                           = 31430 * 2 / 14 = 4490

Word Count (WC) in Bytes   = Number of Words * PPI_Width / 8
                           = 4490 * 16 / 8 = 8980

Adjust blanking WC based on Video mode.

Video mode: Burst Mode

Consistent linetime for Blanking and Active regions is achieved by adjusting blanking word count. Active region has 1 short packet and 4 long packets whereas Blanking region has 1 short packet and 1 long packet. So, 1 Short Packet and 3 Long Packet header, CRC and SSS bytes are reduced from available word count.

For Burst Mode, One line is composed of HSS + HBP + HACT + BLLP + HFP.

Horizontal Sync Start (HSS) -> Short packet -> 2 * (Packet Header + Lanes * SSS) bytes
= 2 * (6 + 2*2) = 20 bytes

Each Long packet without payload-> 2 * (Packet Header + Lanes * SSS) + CRC + Lanes * SSS
= 2 * (6 + 2*2) + 2 + 2*2 = 26 bytes

Total bytes covered in header and footer = 1 * Short packets + 3 * Long packets
                                         = 1 * 20 + 3 * 26 = 98 bytes

Available blanking WC                    = 8980 - 98 = 8882

Divide the total available WC across available blanking parameters HBP and HFP.
Considering a ratio of 1:2 gives: (the values for HBP and HFP are the distribution of the horizontal blanking words across these parameters. In the examples, AMD tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays might have specific requirements. Consult the datasheet for your display).
```
Horizontal Back Porch (HBP)  = 8882 / 3 = 2960.667 = 2961 (rounded) 
Horizontal Front Porch (HFP) = 8882 - 2961 = 5921
```
Set the applicable horizontal timing registers with the preceding calculated values.
```
HBP = 2961 (decimal) = 0xB91
HFP = 5921 (decimal) = 0x1721
```
Divide the total available vertical blanking lines between VSA, VBP, and VFP.
Considering a ratio of 1:1:1 gives: (the values for VSA, VBP, and VFP are the distribution of the vertical blanking lines across these parameters. In the examples, AMD tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays might have specific requirements. Consult the data sheet for your display.)
```
VSA = 5 (decimal) -> 0x05
VBP = 5 (decimal) -> 0x05
VFP = 5 (decimal) -> 0x05
```
Consolidate a set of horizontal and vertical timing parameters for a DSI panel with 640x480@60 fps, 2-Lane, 500 Ms/s, Compressed data of 8-bit width, and Video clock of 21.978 MHz are as follows:
```
HACT = 0x1F4
BLLP (Register 0x50 [15:0]) = 0x8C
HBP  = 0xB91
HFP  = 0x1721

VACT = 0x1E0
VSA  = 0x05
VBP  = 0x05
VFP  = 0x05
```

C-PHY Example Configuration for Burst - C-PHY Example Configuration for Burst - 3.0 English - PG238

MIPI DSI Transmitter Subsystem LogiCORE IP Product Guide (PG238)